Victor Zyuban
ABSTRACT
This paper presents a methodology for unifying the scan mechanism and data retention in latches which leads to scannable latches with the data retention capability achieved at a very low power overhead during the active mode. A detailed analysis of power and area overhead is presented, with layout examples for various common latch styles. Implications of using different power gating techniques for reducing leakage during sleep mode on the design of retention latches are considered, including well biasing for leakage control and sharing wells between gated logic and retention latch devices.
- F. Klass et al. A new family of semidynamic and dynamic flop-flops with embedded logic for high-performance processors. IEEE Journal of Solid-State Circuits, 34(5):712--716, May 1999.Google Scholar
Cross Ref
- S. Mutoh et al. A 1v multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone applications. In ISSCC, pages 168--169, 1996.Google Scholar
- N. Nedovic, M. Aleksic, and V. Oklobdzija. Timing characterization of dual-edge triggered flip-flops. In ICCD, August 2001.Google ScholarCross Ref
- N. Nedovic and V. Oklobdzija. Dynamic flip-flop with improved power. In Proceedings of the International Conference on Computer Design, September 2000. Google ScholarDigital Library
- N. Nedovic and V. Oklobdzija. Hybrid latch flip-flop with improved power efficiency. In Proceedings of the Symposium on Integrated Circuits and Systems Design, 2000. Google ScholarDigital Library
- B. Nikolic et al. Improved sense-amplifier-based flip-flop: Design and measurements. IEEE Journal of Solid-State Circuits, 35(6):876--883, June 2000.Google ScholarCross Ref
- S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada. A 1-v high-speed MTCMOS circuit scheme for power-down application circuits. IEEE Journal of Solid-State Circuits, 32(6):861--869, June 1997.Google ScholarCross Ref
- V. Stojanovic and V. Oklobdzija. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE Journal of Solid-State Circuits, 34(4):536--548, April 1999.Google ScholarCross Ref
- V. Stojanovic, V. Oklobdzija, and R. Bajwa. A unified approach in the analysis of latches and flip-flops for low-power systems. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 227--232, August 1998. Google ScholarDigital Library
- J. Tschanz et al. Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors. In IEEE Symposium on Low Power Electronics and Design, pages 147--152, August 2001. Google ScholarDigital Library
- C. Webb et al. A 400-MHz S/390 microprocessor. IEEE Journal of Solid-State Circuits, 32(11):1665--1675, November 1997.Google ScholarCross Ref
- V. Zyuban and P. Kogge. Application of STD to latch-power estimation. IEEE Transactions on VLSI Systems, 7(1), March 1999. Google ScholarDigital Library
- V. Zyuban and D. Meltzer. Clocking strategies and scannable latches for low power applications. In IEEE Symposium on Low Power Electronics and Design, pages 346--351, August 2001. Google ScholarDigital Library
Index Terms
- Low power integrated scan-retention mechanism
Recommendations
Low power shift register using MTCMOS edge-trigger D flip flop transmission gate in sub-threshold region
MINO'08: Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronicslow power design is most required nowadays due to scaling down the technology where minimizing the voltage level is the most effective way to minimize the power consumption. This paper presents the design and implementation of a low power Complementary ...
Design and optimization of power-gated circuits with autonomous data retention
Power gating has been widely employed to reduce subthreshold leakage. Data retention elements (flip-flops and isolation circuits) are used to preserve circuit states during standby mode, if the states are needed again after wake-up. These elements must ...
A design of low swing and multi threshold voltage based low power 12T SRAM cell
Proposed low power 12T MTCMOS based SRAM cell.Display Omitted A novel low power 12T MTCMOS based SRAM cell is proposed.Charge recycling technique used for reducing the current leakage during transition mode.Use voltage sources to reduce the dynamic ...
Comments