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DAP—a distributed array processor

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Published:09 December 1973Publication History
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Abstract

An array of very simple processing elements is described each with a local semiconductor store. The array may also be used as main storage.

Bit-organisation gives great flexibility, including the minimisation of word length. Use of MSI and LSI is helped by the simplicity of the serial design. Using 15-bit fixed point, the theoretical performance of a 72 × 128 array is about 108 multiplications or 109 additions per second. Comparisons are made with other architectures.

Meteorology is considered as an application. It is attractive to have the whole problem in the array storage.

References

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      • Published in

        cover image ACM SIGARCH Computer Architecture News
        ACM SIGARCH Computer Architecture News  Volume 2, Issue 4
        december 1973
        165 pages
        ISSN:0163-5964
        DOI:10.1145/633642
        Issue’s Table of Contents
        • cover image ACM Conferences
          ISCA '73: Proceedings of the 1st annual symposium on Computer architecture
          December 1973
          169 pages
          ISBN:9781450374286
          DOI:10.1145/800123

        Copyright © 1973 Author

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 9 December 1973

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