S. Hayati
ABSTRACT
This paper presents a method for the generation of controller specifications from high-level behavioral descriptions in control and timing graph form. Input descriptions may contain multiple timing constraints, asynchronous and synchronous inputs, data dependent internal loops, and parallel and conditional branches. The timing graph model is transformed automatically to a state table specification of a synchronous finite state machine. The specification method is effective not only for independent data processors, but also for processors constrained by interface requirements and performing I/O protocol translation. The method has been programmed and tested on selected examples. Results from one example are given along with a comparison with results on the same example from another system.
- 1.E. Girczyc and J. Knight. An ada to standard cell hardware compiler based on graph grammars and scheduling. In Proceedings, 1984 International Corferenee on Computer Design - ICCD, pages 726-729, October 1984.Google Scholar
- 2.J. Nestor and D. Thomas. Behavioral Syuthesis with Interfaces. In IEEE international Conference on CAD, November 1986.Google Scholar
- 3.G. Borriello and R. Katz. Synthesizing Transducers from Interface Specifications. In International Conferer~ce on VLSI, August 1987.Google Scholar
- 4.S. Hayati, A. Parker, and J. Granackl. Representation of control and timing behavior with applications to interface synthesis. In Proceedings of the International Conference on Computer Design, 1988.Google ScholarCross Ref
Index Terms
- Automatic production of controller specifications from control and timing behavioral descriptions
Recommendations
Automatic Derivation of Formal Software Specifications from Informal Descriptions
SPECIFIER, an interactive system which derives formal specifications of data types and programs from their informal descriptions, is described. The process of deriving formal specifications is viewed as a problem-solving process. The system uses common ...
Polychronous controller synthesis from MARTE CCSL timing specifications
MEMOCODE '11: Proceedings of the Ninth ACM/IEEE International Conference on Formal Methods and Models for CodesignThe UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a mathematically expressive model of time, the Clock Constraint Specification Language (CCSL), to specify timed annotations on UML diagrams and thus provides ...
A Specification Translation from Behavioral Specifications to Rewrite Specifications
There are two ways to describe a state machine as an algebraic specification: a behavioral specification and a rewrite specification. In this study, we propose a translation system from behavioral specifications to rewrite specifications to obtain a ...
Comments