Peter Wohl
ABSTRACT
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern generator (ATPG) and are encoded as linear feedback shift register (LFSR) initial values (seeds); one or more patterns can be encoded into a single LFSR seed. During test application, seeds are loaded into the LFSR with no cycle overhead. The method presented achieves reductions of at least 100x in test data and 10x in tester cycles compared to deterministic ATPG while maintaining complete fault coverage, as confirmed by experimental results on industrial designs.
- M. Abramovici, M.A. Breuer, A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.Google Scholar
- E.B. Eichelberger, E. Lindbloom, J.A. Waicukauski, T.W. Williams, Structured Logic Testing, Prentice-Hall, 1991. Google ScholarDigital Library
- V.D. Agrawal, C.R. Kime, K.K. Saluja, "A Tutorial on Built-In Self-Test, Part 1: Principles", IEEE Design & Test 1993, Vol. 10, No.1, pp. 73--82. Google ScholarDigital Library
- G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, J. Rajski, "Logic BIST for Large Industrial Designs: Real Issues and Case Studies", International Test Conference 1999, pp.358--367. Google ScholarDigital Library
- P.H. Bardell, W.H. McAnney, "Self-Testing of Multichip Logic Modules", International Test Conference 1982, pp.200--204.Google Scholar
- P.H. Bardell, W.H. McAnney, J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987. Google ScholarDigital Library
- H.-J. Wunderlich, G. Kiefer, "Bit-Flipping BIST", International Conference on Computer-Aided Design, 1996. Google ScholarDigital Library
- A. Irion, G. Kiefer, H. Vranken, H.-J. Wunderlich, "Circuit Partitioning for Efficient Logic BIST Synthesis", Design and Test Europe, 2001. Google ScholarDigital Library
- B. Könemann, "LFSR-Coded Test Patterns for Scan Designs", European Test Conference, Munich, 1991.Google Scholar
- S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", IEEE Transactions on Computers, Vol. 44, No. 2, Feb. 1995. Google ScholarDigital Library
- S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, "Pattern Generation for a Deterministic BIST Scheme", International Conference on Computer-Aided Design, 1995. Google ScholarDigital Library
- S. Chiusano, S. DiCarlo, P. Prinetto, H.-J. Wunderlich, "On Applying the Set Covering Model to Reseeding", Design and Test Europe, 2001. Google ScholarDigital Library
- N.C. Lai, S.J. Wang, "A Reseeding Technique for LFSR-Based BIST Applications", Asian Test Symposium 2002, pp. 200--205. Google ScholarDigital Library
- B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, D. Wheater, "A SmartBIST Variant with Guaranteed Encoding", Asian Test Symposium 2001, pp. 325--330. Google ScholarDigital Library
- J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.H. Tsai, A. Hertwig, N. Tamarapalli. G. Mrugalski, G. Eide, J. Qian, "Embedded Deterministic Test for Low Cost Manufacturing Test", International Test Conference 2002, pp. 301--310. Google ScholarDigital Library
- J. Rajski, N. Tamarapalli, J. Tyszer, "Automated Synthesis of Phase Shifters for Built-In Self-Test Applications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2000, Vol. 19 No. 10, pp. 1175--1188. Google ScholarDigital Library
- P. Wohl, J.A. Waicukauski, T.W. Williams, "Design of Compactors for Signature-Analyzers in Built-In Self Test", International Test Conference 2001, pp.54--63. Google ScholarDigital Library
- "TetraMAX ATPG", http://www.synopsys.com/products/test/ tetramax_ds.htmlGoogle Scholar
Index Terms
- Efficient compression and application of deterministic patterns in a logic BIST architecture
Recommendations
Scalable selector architecture for x-tolerant deterministic BIST
DAC '04: Proceedings of the 41st annual Design Automation ConferenceX-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. In this paper we introduce a ...
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
This paper presents a new reseeding technique that reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the ...
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the DunesThe claim for new functionalities regarding the improvement of dependability of electronic systems and also the need for managing the time spent during test make the Built-in-Self-Test mechanism (BIST) a promising feature to be integrated in current IC ...
Comments