ABSTRACT
Power consumption is a critical issue in interconnection network design, driven by power- related design constraints, such as thermal and power delivery design. Usually, off-line worst-case power analysis is used in network design to guarantee safe on-line operation, which not only increases system cost but also constrains network performance. In this work, we present an on-line mechanism, called PowerHerd, which can dynamically regulate network power consumption, and guarantee that network peak power constraints are not exceeded. PowerHerd is a distributed approach -- within the interconnection network, each router dynamically maintains a local power budget, controls its local power dissipation, and exchanges spare power resources with its neighboring routers to optimize network performance.Experiments demonstrate that PowerHerd can effectively regulate network power consumption meeting peak power constraints with negligible network performance penalty. Armed with PowerHerd, network designers can focus on system performance and power optimization for the average case rather than the worst case, thus making it possible to employ a more powerful interconnection network in the system.
- S. Borkar. Design challenges of technology scaling. IEEE-MICRO, 19(4):23--20, July/Aug. 1999. Google ScholarDigital Library
- D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In Proc. International Symposium on High Performance Computer Architecture, pages 171--182, Jan. 2001. Google ScholarDigital Library
- X.-N. Chen and L.-S. Peh. Leakage power modeling and optimization of interconnection networks. In Proc. International Symposium on Low Power Electronics and Design, Aug. 2003. Google ScholarDigital Library
- W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In Proc. Design Automation Conference, pages 684--689, June 1999. Google ScholarDigital Library
- J. Duato, S. Yalamanchili, and L. Ni. Interconnection Networks. Morgan Kaufmann Publishers, San Francisco, CA, 2003. Google ScholarDigital Library
- E. Grochowski, D. Ayers, and V. Tiwari. Microarchitectural simulation and control of di/dt-induced power supply voltage variation. In Proc. International Symposium on High Performance Computer Architecture, pages 7--16, Feb. 2002. Google ScholarDigital Library
- R. Joseph, D. Brooks, and M. Martonosi. Control techniques to eliminate voltage emergencies in high performance processors. In Proc. International Symposium on High Performance Computer Architecture, pages 91--102, Feb. 2003. Google ScholarDigital Library
- S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb. The Alpha 21364 network architecture. IEEE Micro, 22(1):26--35, Jan./Feb. 2002. Google ScholarDigital Library
- R. H. Myers. Classical and Modern Regression with Application. Duxbury Press, Boston, MA, 1989.Google Scholar
- C. Patel, S. Chai, S. Yalamanchili, and D. Schimmel. Power-constrained design of multiprocessor interconnection networks. In Proc. International Conference on Computer Design, pages 408--416, Oct. 1997. Google ScholarDigital Library
- RLX. Features of Server Blades Design. http://www.rlx.com.Google Scholar
- L. Shang, L.-S. Peh, and N. K. Jha. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proc. International Symposium on High Performance Computer Architecture, pages 79--90, Feb. 2003. Google ScholarDigital Library
- K. Skadron, T. Abdelzaher, and M. R. Stan. Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management. In Proc. International Symposium on High Performance Computer Architecture, pages 17--28, Feb. 2002. Google ScholarDigital Library
- M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, J.-W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal. The RAW microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE-MICRO, 22(2):25--35, Mar./Apr. 2002. Google ScholarDigital Library
- H.-S. Wang, X.-P. Zhu, L.-S. Peh, and S. Malik. Orion: A power-performance simulator for interconnection networks. In Proc. International Symposium on Microarchitecture, pages 294--305, Nov. 2002. Google ScholarDigital Library
- F. Worm, P. Ienne, P. Thiran, and G. De Micheli. An adaptive low power transmission scheme for on-chip networks. In Proc. International System Synthesis Symposium, Oct. 2002. Google ScholarDigital Library
- T. T. Ye, L. Benini, and G. De Micheli. Analysis of power consumption of switch fabrics in network routers. In Proc. Design Automation Conference, pages 524--529, June 2002. Google ScholarDigital Library
- L.-T. Yeh and R. C. Chu. Thermal Management of Microelectronic Equipment: Heat Transfer Theory, Analysis Methods, and Design Practices. ASME Press, New York, NY, 2002.Google Scholar
Index Terms
- PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
Recommendations
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks
As interconnection networks proliferate to a wide range of high-performance systems, power consumption is becoming a significant architectural issue. In interconnection networks, the peak-power consumption directly affects the solution for package ...
Short-circuit power driven gate sizing technique for reducing power dissipation
One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order ...
Power saving in regular interconnection networks
The high level of computing power required for some applications can only be achieved by multiprocessor systems. These systems consist of several processors that communicate by means of an interconnection network. The huge increase both in size and ...
Comments