ABSTRACT
A block placement program and a routing program for inter-block connection of master-slice LSI's are described. The placement program reduces the total expected wire length, by iterative improvements of block placement and gate assignment to blocks. The routing program employs Lee's algorithm basically, and modifications have been made to increase wirability and reduce computer time. The results of applying these programs to several types of LSI's are presented.
- 1.A. Masaki, Y. Harada, T. Chiba, "200-Gate ECL Master-Slice LSI", ISSCC Digest of Technical Papers, February 1974, pp. 62-63.Google Scholar
- 2.Y. Ikemoto et al., "Correction and Wiring Check System for Master-Slice LSI," to be published in this issue. Google ScholarDigital Library
- 3.S. Goshima, Y. Ishibashi, A. Osawa, "A Placement Program for Printed Circuit Board," USA-Japan Design Automation Symposium Proceedings, August 1975, pp. 95-99.Google Scholar
- 4.P. W. Case et al., "Solid Logic Design Automation," IBM J. Res. and Dev., vol. 8, April 1964, pp. 127-140.Google ScholarDigital Library
- 5.C. Y. Lee, "An Algorithm for Path Connections and Its Applications," IRE Trans. on Electronic Computers, Vol. EC-10, No. 3, September 1961, pp. 346-365.Google ScholarCross Ref
- 6.J. H. Hoel, "Some Variations of Lee's Algorithm IEEE Trans. on Computers", Vol. C-25, No. 1, January 1976, pp. 19-24.Google Scholar
Index Terms
- Placement and routing program for master-slice LSI's
Recommendations
On the relation between wire length distributions and placement of logic on master slice ICs
DAC '84: Proceedings of the 21st Design Automation ConferenceThe quality of placement and routing on gate arrays is commonly measured by average wire length. With regard to wire length, placement and routing are mutually competing tasks and the solution space for both is exponential. Estimates of measures of ...
Routing-architecture-aware analytical placement for heterogeneous FPGAs
DAC '15: Proceedings of the 52nd Annual Design Automation ConferencePlacement is a crucial stage for FPGA implementation. Most FPGA placers optimize their placement results by minimizing half-perimeter wirelength (HPWL). Due to the segmented routing architecture in FPGAs, however, the HPWL function cannot model routed ...
Comments