ABSTRACT
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter variations for sub-100nm technologies to produce an upper bound prediction on timing, it is equally important to consider the correlation of these variations for the bound to be useful. In this paper we present an efficient block-based statistical static timing analysis algorithm that can account for correlations from process parameters and re-converging paths. The algorithm can also accommodate dominant interconnect coupling effects to provide an accurate compilation of statistical timing information. The generality and efficiency for the proposed algorithm is obtained from a novel simplification technique that is derived from the statistical independence theories and principal component analysis (PCA) methods. The technique significantly reduces the cost for mean, variance and covariance computation of a set of correlated random variables.
- M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits," ICCAD-2000, pp. 62--67, November 2000. Google ScholarDigital Library
- S. Tsukiyama, M. Tanaka, and M. Fukui, "A New Statistical Static Timing Analyzer Considering Correlation Between Delays," in Proc. TAU, pp. 27--33, Dec 2000. Google ScholarDigital Library
- J. A. G. Jess and K. Kalafala et al, "Statistical timing for parametric yield prediction of digital integrated circuits", Design Automation Conference (DAC), pp. 932--937, June 2003. Google ScholarDigital Library
- H. Chang and S. S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-like Transerval", ICCAD 2003, pp. 621--625, Nov 2003. Google ScholarDigital Library
- Aseem Agarwal, David Blaauw, Vladimir Zolotov and Sarma B. K. Vrudhula, "Statistical Timing Analysis Using Bounds", DATE 2003, pp. 10062--10067. Google ScholarDigital Library
- Anirudh Devgan and Chandramouli Kashyap, "Block-based Static Timing Analysis with Uncertainty", ICCAD 2003, November 2003. Google ScholarDigital Library
- Aapo Hyvarinen, "Survey on Independent Component Analysis", Helsinki University of Technology, Lab of Computer and Information Science, Finland.Aapo Hyvarinen, "Survey on Independent Component Analysis", Helsinki University of Technology, Lab of Computer and Information Science, Finland.Google Scholar
- R. Arunachalam, K. Rajagopal and L. Pileggi, "TACO: Timing Analysis with Coupling" Proceedings of the Design Automation Conference, pp. 266--269, June 2000. Google ScholarDigital Library
- Sani R. Nassif, "Modeling and Analysis of Manufacturing Variations", IEEE 2001 Custom Integrated Circuits Conference, pp. 223--228.Google Scholar
- Min Cao, "Static Timing Analysis in Presence of Process Variations", Ph.D dissertation, ECE Department, Carnegie Mellon University, 2002.Google Scholar
- C.E. Clark, "The Greatest of a Finite Set of Random Variables", Operations Research, vol. 9 pp. 85--91, 1961.Google ScholarDigital Library
Index Terms
- STAC: statistical timing analysis with correlation
Recommendations
Correlation-aware statistical timing analysis with non-gaussian delay distributions
DAC '05: Proceedings of the 42nd annual Design Automation ConferenceProcess variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The Non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. ...
Explicit computation of performance as a function of process variation
TAU '02: Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systemsEach manufactured chip is a little bit different, and designers want as many as possible of these chips to work. Process variation is a function of many variables, as the width, thickness, and inter-layer thickness can vary independently for each layer ...
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and designFluctuations in intrinsic linear Vt, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic σVT, free of extrinsic process, length and width variations, is random, ...
Comments