Channel-Length-Dependence of Strain Field in Transistor Studied via Scanning Moiré Fringe Imaging

Strain engineering is routinely applied in the fabrication of advanced semiconductor devices to enhance the mobility of the carriers in transistors.^1,2 The mobility of electrons or holes is boosted when the channel in a transistor is under either a tensile or compressive strain, respectively. The Si_1−xC_x embedded in the source/drain region has been used for n-type field effect transistors.³ The lattice parameter of Si_1−xC_x with a carbon concentration of about 1% is smaller than that of pure Si. Thus, a compressive stress is formed in the source/drain region, which in turn induces a tensile strain in the n-type channel.⁴ Since the electrical performance of the device is greatly influenced by the strain field induced in the channel region, it is required to control the strain field for optimum manufacturing processing. Furthermore, with decrease in the size of modern semiconductor devices, the strain field in the semiconductor devices tends to be strongly influenced by layout design parameters such as the channel length and the geometry of the source and drain regions.^5,6 Therefore, for next-generation technology, it is required to monitor the layout-dependent strain behavior with high precision at nanometer-scale spatial resolutions. Although various tools have been applied to the measurement of strain fields in semiconductor structures,^4,7–17 there have been relatively few experimental results regarding studying the effect of the channel length on the strain field induced in semiconductor device structures.¹⁸

In this study, we have applied scanning moiré fringe (SMF) imaging,¹⁹ which is a high-angle annular dark-field scanning transmission electron microscope (HAADF-STEM)-based technique, to quantitatively measure the strain field in transistors with various channel lengths down to 25 nm. SMF imaging is a recently developed method that can measure strain fields at a high spatial resolution in the nanometer scale.^20–22 In the HAADF-STEM experiment, the SMFs appear when the scanning grating size d_s is close to the crystal lattice spacing d_l. Figure 1a shows the strained lattice spacing d_l that increases from the bottom to the top of the pattern. Figure 1b shows the scanning grating spacing d_s wherein d_l < d_s. The strained lattice (spacing d_l) superposed on the scanning grating (spacing d_s) gives rise to SMFs shown in Fig. 1c.²² Because the SMF spacing d_SMF changes very sensitively to the variation in the lattice plane spacing d_l, the strain field can be obtained by substituting the measured d_SMF and a calibrated value of d_s in the formula for the width of the translational moiré fringe.²⁰

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Dummy transistors with channel lengths down to 25 nm were manufactured using Si_1−xC_x (x = 0.01) source and drain stressors to introduce uniaxial tensile strain to n-type channels below the gates. Phosphorus atoms were doped into the source and drain regions by using phosphine (PH₃) as a doping gas. The channel lengths in the transistors were varied with fixed parameters such as the size and shape of the source/drain. The specimens were prepared by using a focused ion beam at 30 eV, and followed by final milling at 2 keV to reduce the thickness of the amorphous layers. In order to minimize strain relaxation, the specimen thicknesses were fixed to about 250 ± 10 nm for the [110] zone axis. The SMF images of the specimen were acquired using an image/probe Cs-corrected TEM equipped with a Gatan annular dark-field detector. A DCOR aberration-corrector enabled us to generate an electron probe of diameter 0.7 Å in the STEM mode. The convergence semi-angle of the probe and the detector's inner semi-angle were 22 mrad and 45 mrad, respectively. We confirmed that the detector's inner angle of 45 mrad allowed us to obtain STEM image in HAADF regime.²¹

The SMF images shown here were acquired at a magnification of 640 K with an acquisition time (dwell time) of 2 μs for each pixel. In order to obtain strain maps parallel to the strained channel, the translational SMFs formed by interfering scanning grating with the (220) lattice d-spacing of Si crystal were obtained and examined. The SMF images shown here were recorded from one acquisition with a scanning grating size of d_s = 0.1982 nm, which was determined by a calibration with a measurement error of 0.05%. The detailed process for the calibration is reported in a previous study.²⁰

Figure 2a shows the SMF spacing d_SMF as a function of the strain in the crystal lattice. The SMF spacing was calculated with d_s = 0.1982 nm (d_l < d_s) based on the formula for the width of the translational moiré fringe.²⁰ Positive values along the horizontal axis denote tensile strain and negative values denote compressive strain. The SMF spacing d_SMF increases as the lattice spacing increases due to tensile strain. The gradient in the curve increases as tensile strain is applied to the crystal lattice plane. Therefore, the advantage of using the condition d_l < d_s is that tensile strain can be more sensitively detected than compressive strain.²² However, the increase in d_SMF corresponding to the applied tensile strain degrades the spatial resolution R_s (R_s = d_SMF). Thus, for obtaining the improved spatial resolution required for the measurement of tensile strain fields applied in a short-channel transistor, we can acquire SMF imaging under the condition of d_l > d_s by reducing the scanning grating size d_s. In this experiment, as described in a later section, the SMF spacing measured in the strained-channel regions was less than 8 nm. In this study, the strain profile was extracted by direct measurement the two spacing of the SMFs in the image, which corresponds to a spatial resolution of 16 nm. Although the spatial resolution can be improved when d_l > d_s, we obtained SMF images under the condition of d_l < d_s (d_s = 0.1982 nm) since a spatial resolution of 16 nm is sufficient even for the strain measurement of the transistor with a very short channel length of 25 nm.

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Figures 2b–2f shows SMF₂₂₀ images for five transistors with various channel lengths down to 25 nm. The SMFs observed in the channel region below the gate are curved due to the strain field introduced during the manufacturing process of embedding the Si_1−xC_x (x = 0.01) stressor in source and drain regions. In addition, the SMF spacing d_SMF is observed to increase from the Si substrate toward the channel (from bottom to top of the image). Since the SMF images in the experiments were acquired with d_l < d_s, the increase in the SMF spacing d_SMF in the SMF images represents a tensile strain field existing in the lattice.²⁰ Therefore, from the SMF images, we can intuitively and qualitatively infer that the channel region just below the gate is under tensile strain without the need of any further interpretation of the image. In order to perform quantitative measurement of the strain fields, we measured the SMF spacing d_SMF along the [001] direction, as indicated by the dashed line in Fig. 2f. Subsequently, based on the curve shown in Fig. 2a, the measured SMF spacing values of d_SMF in each case were converted into quantitative values of strains as plotted in Fig. 3. Here, positive values along the vertical axis denote tensile strain. For all transistors, the strains in the Si substrate at a distance of almost 100 nm away from the channel region were measured to be zero (0 ± 0.05%). This indicates that the influence of the stressors almost disappears at a depth of about 100 nm from the channel.

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For transistors with the channel lengths greater than 35 nm, the strain field increases progressively toward the channel and reaches a maximum at the channel region immediately below the gate. However, the strain field in the transistor with the very short channel length of 25 nm showed a different behavior compared with that of the other transistors; this can be observed from the strain profiles shown in Fig. 3. For the 25-nm transistor, the d_SMF begins to reduce from the 20 nm depth as can be seen in Fig. 2b whereas the d_SMF was increased progressively toward the gate for all of the transistors except the 25 nm-transistor.

Figure 4 shows the measured strain values in the channel region just below the gate as a function of the channel length down to 25 nm. The strain field in the channel is found to increase as the gate length decreases, and it reaches a maximum at the channel length of L_Ch = 35 nm. However, the strain field in the channel region begins to decrease as the channel length L_Ch further decreases below ∼35 nm. The 25-nm-channel transistor in Fig. 3, the area where the strain reaches its maximum has the narrowest lateral distance between the source and drain due to their shapes. Therefore, for the transistor with channel length below 35 nm, the decrease in the strain field in the channel region is attributed to the geometry of the source and drain regions.

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We have demonstrated that scanning moiré fringe imaging is a powerful tool for the quantitative measurement of the strain fields formed in transistor channel regions at nanometer-scale spatial resolution. By investigating the strain field in transistors with various channel lengths, we found that the strain in the channel increases up to 0.7 ± 0.1% as the channel length shrinks to 35 nm. We observed that the strain field in the channel region decreases for transistors with channel lengths below 35 nm, thereby indicating that the geometry of the source and drain plays a role in the development of the strain field for short-channel transistors. By applying methods such as SMF imaging for strain measurement, it is possible to determine the optimum layout design for the strain field formed during manufacturing processes to enhance the electrical performance in transistors with channel lengths of 25 nm and below.

Acknowledgments