Editors' Choice—2.32 kV Breakdown Voltage Lateral β-Ga₂O₃ MOSFETs with Source-Connected Field Plate

Most electrical parameters such as pinch-off voltage (V_p), specific on-resistance (R_on,sp.), I_on/I_off ratio, current density (A/mm) and V_BR of the power MOSFETs are mainly determined by the channel design. Since this is our first device process, we have intuitively determined the epitaxial layer growth method and channel layer design based on the experience of the gallium arsenide (GaAs) power metal-semiconductor field-effect transistors (MESFETs). First, Fe-doped semi-insulating (010) β-Ga₂O₃ substrate and ozone MBE method were used to reduce substrate leakage current during operation of high power MOSFETs and increase the controllability of growth parameters of Si-doped thin β-Ga₂O₃ homoepitaxial channel layer.

In the channel design, we increased the doping concentration to order of 10¹⁸ cm⁻³ to form ohmic contacts without additional process, such as selective ion implantation with annealing and epitaxial layer regrowth with etching, at source and drain regions to improve ohmic contact properties. On the other hand, the channel layer thickness was reduced to much thinner than those of previous reported devices to decrease the pinch-off voltage of the device. The channel layer thickness (150 nm) and Si donor concentration (1.5 × 10¹⁸ cm⁻³) were verified by electrochemical capacitance-voltage (ECV) measurement as-grown at Novel Crystal in Japan. The Fe-doped semi-insulating (010) substrates used for epitaxial growth were grown by the edge-defined, film fed growth (EFG) method. At the current technology level, the maximum available wafer size is 10 mm × 15 mm and used for device fabrication in this work.

The device fabrication began with a custom-made epi wafer and a monitor of unintentionally doped (UID) Ga₂O₃ piece with same size. A 20 nm Al₂O₃ dielectric was deposited on the Ga₂O₃ free surface before starting process to keep original clean surface as-grown by plasm-enhanced atomic layer deposition (PEALD) at 300°C, which served as both the gate dielectric and channel pre-passivation. Device isolation was carried out with an inductively coupled plasma (ICP) reactive ion etch (RIE) using BCl₃/N₂ mixed gas chemistry. The composition of mixed etch gas was 12.5% N₂ in BCl₃ and the chamber pressure was fixed at 5 mTorr. The RF bias power was adjusted as low as 10% of ICP coil power to reduce plasma particle damage. Under these conditions, the mesa etched angle was about 150 degree, which was suitable for removing disconnection issue of metal lines that cross over the mesa etched channel region. Al₂O₃ layer in the source and drain regions was removed for ohmic metal contact to Ga₂O₃ using buffered oxide solution. Then source-drain ohmic contacts of the transistor were formed by depositing a Ti/Au (25/300 nm) metal layer using an E-beam evaporator and then annealing for 1 minute at 475°C in a nitrogen (N₂) ambient. Circular transmission line method (C-TLM) was used to evaluate metal-semiconductor ohmic contact property. Unlike expectations, specific contact resistivity (ρ_c) was as high as 6.0 × 10⁻³ Ω⋅cm². So, selective ion implantation and/or epitaxial regrowth process will be tried to improve ohmic contact properties in the next process.

After gate patterning and wafer cleaning with diluted HCl solution, the sample was deposited using a Ti/Au (25/300 nm) metal stack at pressure < 1 × 10⁻⁷ Torr. The gate-connected, source-connected, and drain-connected field plates are already well known as FP technologies in lateral GaN-based RF and power devices to increase their breakdown voltages. In particular, at low frequencies, the source-connected FP is more suitable for increasing the uniformity of the electric field profile across gate region and lowering peak electric field at the drain-side edge of the gate in the lateral GaN/AlGaN HEMTs. Because this characteristic might reduce the probability of breakdown at weaker points of the device, a source-connected FP structure, which is different from those of the previous reports, was applied in this work. Source-connected FP length (L_FP) was designed to be 3 μm.

After checking the basic device characteristics, a 300 nm SiO₂ field-plate dielectric film was grown by plasm-enhanced chemical vapor deposition (PECVD) at 300°C. This dielectric was used to serve a dual functionality for field-plate mechanical support as well as device surface passivation including mesa etched area. The dielectric via holes were formed by a CF₄-based ICP RIE method and then a thick Ti/Au (20/450 nm) field plate metal was deposited for facilitating pad probing during measurement and reducing electrical resistance of the devices. Finally, all the devices were passivated with a 200nm Si₃N₄ dielectric layer by PECVD and then probing pads were opened by ICP RIE.

A cross-sectional view of β-Ga₂O₃ MOSFET with source-connected FP and MBE-grown epitaxial layers used in this work is shown in Fig. 1a. Three different dielectric films of Al₂O₃, SiO₂, and Si₃N₄ are used for the high voltage device fabrication. The uppermost layer (dark green) of 200 nm Si₃N₄ film is used for final passivation and its description is not shown in this figure. Fig. 1b shows an optical microscope of finger-type MOSFET taken after gate electrode formation and basic d.c. parameter measurements. Fig. 1c shows a top-down SEM image of a lateral MOSFET with source-connected FP structure cross-over the gate finger. This corresponds to the region indicated by the dotted line in Fig. 1b. Device parameters are unit gate width (W_g) of 100 μm, gate length (L_g) of 3 μm, field plate length (L_FP) of 3 μm, and gate-drain spacing (L_gd) of 5, 10, 15, 20, and 25 μm. Fig. 1d shows cross-sectional SEM view of the source, gate, drain and FP shapes of a source-connected FP-MOSFET with L_g = 3 μm, L_FP = 3 μm, and L_gd = 15 μm, obtained from the focused ion beam (FIB) analysis. The L_gd and L_FP, which mainly affect the breakdown voltage of the device, are formed about 14 μm (∼1 μm narrow) and about 3.3 μm (∼10% larger), respectively. Since the real L_gd value of the device was narrower than that of the designed one, if the E_BR calculation is performed based on actual L_gd, the E_BR values will be higher than those shown in Fig. 4. Therefore, the designed values are used for convenience of calculation of the E_BR with the L_gd of MOSFETs in this work.

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DC output current-voltage (I-V) characteristics of the fabricated source-connected FP-MOSFET with L_g = 3 μm, L_FP = 3 μm, and L_gd = 25 μm were measured with an HP 4156B semiconductor parameter analyzer on a Cascade probe station at room temperature under air atmosphere conditions and shown in Fig. 2. Fig. 2a shows DC output family curves from V_gs = + 1 V to V_gs = −7 V with a gate voltage step of −1V. Fig. 2b and Fig. 2c show semi-log and linear scale transfer characteristics measured from V_gs = + 3 V to V_gs = −15 V with a gate voltage step of −0.05 V and at a constant V_DS = 30 V, respectively. The I_on/I_off ratio was estimated as high as 10⁷. The pinch-off voltage, which is defined by a drain current density of 100 nA/mm,³ is typically observed around −4.6 V. The device shows a peak g_m of 2.55 mS/mm at V_gs = + 1.3 V. The drain current density at V_gs = + 3 V and V_DS = 30 V is typically around 10 mA/mm, as shown in Fig. 2b and Fig. 2c.

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The three-terminal off-state breakdown characteristics were measured with a Keithley Tektronix 371A High Power Curve Tracer. For the breakdown measurements, the devices were submerged in Fluorinert FC-770 to reduce air breakdown potential. Before breakdown test, we checked the leakage current level of the devices at V_GS = −10V and V_DS = + 30 V conditions. All leakage current levels of drain and gate were lower than 1.5 × 10⁻⁸ A. The system compliance was adjusted to 10 μA (∼ × 1000 higher than original leakage current) based on our own reference to protect the system during the catastrophic breakdown of the device and this value was used as a device breakdown criteria. The drain voltage was swept from 0 V to 3 kV with a voltage step of 2 V at a constant V_gs = −10 V. For a device with L_gd = 25 μm, the catastrophic breakdown was occurred at 2321 V as shown in Fig. 3a. This is the highest record of V_BR measured in a lateral FP Ga₂O₃ MOSFET to date. The V_BR for L_gd = 5 μm, 10 μm, and 20 μm were also measured with the same criteria of 10 μA and shown with L_gd = 25 μm in Fig. 3b.

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Figure 4 shows V_BR and E_BR vs. L_gd of the measured devices in this work. The experimental E_BR is simply calculated by dividing V_BR over L_gd as mentioned reason in previous experimental section. The V_BR was monotonically increased with L_gd. The E_BR for a device with L_gd = 25 μm was 0.93 MV/cm and other devices also have values near 1 MV/cm, which is similar with reported data by K. Zeng et al.²⁰ However this is very low compared to the expected β-Ga₂O₃ E_BR of 6 − 8 MV/cm,² 3.8 MV/cm for L_gd = 0.6 μm,³ and 5.2 MV/cm for 181 nm-thick β-Ga₂O₃.⁴ This means that as the L_gd increases, the breakdown occurs at weaker points such as the dielectric films and FP edge rather than the breakdown of the Ga₂O₃ itself. In order to utilize the intrinsic E_BR of the Ga₂O₃ channel layer, the dielectric materials used below and above the FP should have large dielectric constant and/or enough thickness.

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Figure 5 shows a comparison of R_on,sp vs. V_BR of device figure of merit (FOM) against previously reported lateral Ga₂O₃ MOSFETs relative to the theoretical limits of Si, GaN and Ga₂O₃. Developed a source-connected lateral β-Ga₂O₃ FP-MOSFET with L_gd = 25 μm showed a record high V_BR of 2321 V and a R_on,sp of 959 Ω·cm². This good result is attributed to the optimization of process conditions of plasma enhanced atomic layer deposition (PEALD) of Al₂O₃ gate dielectric²¹ and the passivation schemes with internal SiO₂ and external Si₃N₄ dielectric films by PECVD in the device structure as shown in Fig. 1a. Another device with L_gd = 20 μm also showed a high V_BR of 1871 V. Previous reported FP β-Ga₂O₃ MOSFET with same L_gd = 20 μm showed a high V_BR of 1850 V and a R_on,sp of about 2100 Ω·cm².²⁰ Our device shows as high as V_BR but very low R_on,sp. This is due to a high doping concentration (1.5 × 10¹⁸ cm⁻³) of the channel. It is noted that high performance power MOSFETs with low R_on,sp and high V_BR could be implemented with increasing doping concentration of the thin channel and adopting source-connected FP structure described in this work. In addition to high electrical performances of the Ga₂O₃-based MOSFETs and SBDs and its excellent material properties, the promising low cost and large-size β-Ga₂O₃ substrates produced from melt-grown method as well as the high speed epitaxial layer growth techniques can reduce the whole cost of power devices and hence making it possible for commercial products in near future.^13,22,23

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High performance lateral β-Ga₂O₃ MOSFETs with source-connected field plate are demonstrated on Si-doped thin channel layer grown by MBE on Fe-doped semi-insulating β-Ga₂O₃ bulk substrate. A record-high three-terminal off-state breakdown voltage of more than 2.32 kV is measured in source-connected FP lateral β-Ga₂O₃ MOSFETs with a gate-drain spacing L_gd = 25 μm and a field plate length L_FP = 3 μm. The results indicate that source-connected FP lateral β-Ga₂O₃ MOSFETs are very promising candidates for next generation high-voltage and high-power switching devices applications above 2 kV. In conclusion, source-connected FP technology provides a stable, low cost and effective way to make high breakdown voltage in lateral β-Ga₂O₃ MOSFETs.

This work was supported by "The Strategic Core Material Development Program (No. 10080736)" of the Ministry of Trade, Industry & Energy (MOTIE), Korea. We thank Dr. In-ho Kang of Korea Electrotechnology Research Institute (KERI) for his support high voltage breakdown measurements.

Jae Kyoung Mun 0000-0002-1849-2117

Hyun-Wook Jung 0000-0001-5770-6387