Research on Interface Properties of Thermally Grown SiO₂ and ALD SiO₂ Stacked Structures

We fabricated MOS capacitors to study SiO₂/4H-SiC interface properties. Samples used in the experiments were commercially available n-type epitaxial 4° off-axis oriented 〈11–20〉 SiC wafers with Si-plane (0001) orientation, an epitaxial layer thickness of 10 um, and a doping concentration of 8 e15 cm⁻³. First, the samples were cleaned using the Radio Corporation of America process. Then, the sacrificial oxide layer was grown and rinsed off with 10% HF to remove contaminants and the nature oxide layer while simultaneously reducing the surface roughness of the wafers. Second, some samples were oxidized in an O₂ atmosphere at 1400 °C for 2 min, followed by a NO annealing process at 1200 °C for 70 min. After thermal oxidation, the sample underwent NO annealing and underwent reoxidation phenomenon, so the thickness of thermal SiO₂ was thick. The average thickness of SiO₂ was measured to be 15 nm using ellipsometry, followed by ALD SiO₂ deposition process, resulting in a final total SiO₂ thickness of 48 nm, the temperature of the ALD process was 300 °C, the precursor used was ozone and di-isopropylaminosilane (DIPAS, C₆H₁₇NSi), with N₂ gas used as a carrier gas. The remaining samples underwent a process of dry oxygen oxidation at 1400 °C for 13 min and annealed at 1200 °C for 70 min; SiO₂ thickness was measured to be approximately 55 nm. Both samples underwent NO annealing process. Third, aluminum electrodes and backside electrodes were grown using a sputtering process. The measurement pattern was made through photolithographic process with an electrode thickness of 1 μm, the area of metal electrode was 2.54 × 10⁻⁴ cm², all electrical characteristics were obtained using Keysight B1505 measurement analyzer, and we measured capacitance-voltage (C–V) and current-voltage (I-V) electrical characteristics.

The schematics of the stacked and thermal SiO₂ structures are shown in Fig. 1. There are no voids between the ALD stacking SiO₂ and thermal SiO₂. Owing to the high oxidation temperature, excessively short oxidation times can result in uneven distribution of oxygen gas in the reaction chamber, resulting in poor uniformity of oxidation film; therefore, a 2 min oxidation condition is reasonable, with the final oxidation film thickness being approximately 15 nm. The oxidation rate of thermal SiO₂ gradually decreases with the increase of oxide film thickness. For a thin thermal oxidation layer, the oxidation reaction rate is higher, which can effectively reduce the interface defects between SiO₂ and SiC. Oxygen gas in the reaction chamber should be uniformly distributed, and the oxidation time should be as short as possible, and the thickness of the thermal oxidation film should be as thin as possible. Moreover, the thickness of SiO₂ is strongly correlated with the interface states density. ¹⁷ Therefore, when the thermal SiO₂ film is relatively thin, the oxidation reaction rate can be increased to reduce interface defects. The high-frequency C–V curves of the two MOS capacitor samples are shown in Fig. 2. The theoretical curves of the MOS capacitors are also added for comparison, and the C–V characteristics were obtained at 1 MHz with a voltage sweep step of 0.1 V in the scanning from −10 V (deep depletion region) to 10 V (the accumulation region). Figure 2 shows that the flatband voltage of the stacked structure tends to drift slightly to the left compared with the theoretical curve, indicating that positive charges are trapped by the donor-like oxide film defects, resulting in the hole injection phenomenon. In contrast to high temperature thermal oxidation reaction, ALD has a low process temperature. Further, silicon and oxygen elements generated by the decomposition of precursor are adsorbed onto the thermal oxidation film, which reacts to generate silicon oxide. Simultaneously, the products of precursor decomposition also generate hydroxide radical. At the same time, under similar ALD process conditions with the same precursor, oxygen vacancies have been detected via X-ray photoelectron spectroscopy. ^18,19 Herein, oxygen vacancies exhibit donor like traps, capturing positive charges. Consequently, the flatband voltage of a stacked structure is more negative than that of thermal oxidation structure. The C–V frequency dispersion characteristics of the thermal SiO₂ structure and ALD stacked structure at the measurement frequencies of 1, 10, 100, and 1 MHz are shown in Figs. 3a and 3b. Figure 3 shows that the frequency dispersion characteristics of the stacked structure are not significantly different from that of the thermal SiO₂ structure, indicating that the interface quality of the stacked structure has not been compromised. Meanwhile, a bulging phenomenon, which is the result for appearance of deep energy level traps in the oxide film, was observed. According to the relationship between surface potential and SiC energy level, the bulge was approximately 1–2 eV below the SiC conduction band energy. However, no bulging was observed in the C–V curve of thermal oxidation structure. We believe that bulging is caused by oxygen vacancy defects in the ALD film, oxygen vacancy defects capture hole carriers and causing abnormal changes in the multi frequency C–V curve. The essence of bulging phenomenon has also been mentioned in other studies. ²⁰ The following section presents a further discussion on oxidation film defects. Figure 4 shows the C–V hysteresis characteristics curves of two structures, the C–V curves scans from the negative voltage depletion state to the positive voltage accumulation state and vice-versa. The C–V characteristic of the stacked structure shifted significantly to the left during the reverse scanning process, whereas the C–V characteristic of the thermal oxidation film shifted slightly to the right. This also proves that the defect type of the two oxidation films were different.

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The distribution of the interface states density along the conduction band energy level extracted using a high-frequency and quasi-static method is shown in Fig. 5. Quasi-static C–V characteristic measurement involves the application of a very slow (<0.1 V S⁻¹) time-varying voltage signal linearly increasing over time to the gate electrode, simultaneously using a sensitive ammeter to measure the current flowing through the MOS capacitor. Based on the amplitude of changes in gate current and gate voltage, the quasi-static capacitance can be obtained, which is calculated using Eq. 1.

$$\begin{eqnarray}&&C=\displaystyle \frac{{I}_{g}}{\tfrac{d{V}_{g}}{dt}}\end{eqnarray} \tag{ 1 }$$

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Herein, the interface states density of the stacked structure is further reduced compared with the thermal SiO₂ structure at 0.2 eV below the conduction band energy level. In contrast to the thermal SiO₂ structure, the stacked structure can reduce the interface states density by two times. Moreover, a steeper decreasing trend of D_it along the energy level is observed, which is consistent with the theory that reducing SiO₂ film thickness can increase the thermal oxidation rate. Therefore, this approach can be considered for device fabrication to reduce the thermal budget while reducing interface defects. This stacked structure provides a new method for replacing the thermally oxidized gate dielectric film of SiC MOSFET and may improve power device performance.

The leakage characteristics of the two samples were also analyzed by continuously applying a gradually increasing gate voltage to the samples until their breakdown. Moreover, the relationship between the current density and electric field is shown in Fig. 6.

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The electric field is obtained using Eq. 2:

$$\begin{eqnarray}&&{E}_{ox}=\displaystyle \frac{{V}_{g}-{V}_{fb}}{{t}_{ox}},\end{eqnarray} \tag{ 2 }$$

where ${V}_{g}$ is the gate voltage, ${V}_{fb}$ is the flatband voltage, and ${t}_{ox}$ is the thickness of the oxide film. The Fowler–Nordheim current is defined using Eq. 3, where ${A}_{G}$ is the gate area, and ${E}_{ox}$ is the gate electric field. A and B are the coefficients, obtained using Eqs. 4 and 5.

$$\begin{eqnarray}&&{I}_{FN}={A}_{G}\ast A\ast {{E}_{ox}}^{2}\ast \exp \left(\frac{-B}{{E}_{ox}}\right)\end{eqnarray} \tag{ 3 }$$

$$\begin{eqnarray}&&A=\displaystyle \frac{{q}^{3}\left(\tfrac{m}{{m}_{ox}}\right)}{8\pi h{\varnothing }_{B}}\end{eqnarray} \tag{ 4 }$$

$$\begin{eqnarray}&&B=\displaystyle \frac{8\pi \sqrt{2{m}_{ox}{{\varnothing }_{B}}^{3}}}{3qh}\end{eqnarray} \tag{ 5 }$$

Figure 6 shows the I–V curves of the stacked SiO₂ structure and thermal oxidized sample measured at room temperature 25 °C. For thermal oxidized sample, electrons would accumulate at the SiO₂/4H-SiC interface because of a positive bias. Moreover, electrons cross barrier height through Fowler–Nordheim tunneling. The barrier height of SiO₂/SiC obtained through the F–N current formula is 3.05 eV. For stacking SiO₂ sample, a faster increase in current can be observed starting from 5 MV cm⁻¹, the oxidation film grown by ALD produced different types of defects, which results in a differently shaped I-V curve compared to the thermal oxidation structure I-V curve. We used model parameter fitting methods to determine the current conduction mechanism in different electric field. The leakage current in the low electric field range included trap assisted tunneling (TAT), ^21,22 hopping conduction. ^23,24 Fowler Nordheim (F–N) tunneling, and Poole Frenkel (P–F) effect, which are the leakage mechanisms observed in the high electric field range. ^25,26 We confirmed that in the low electric field range, TAT and hopping conduction were the current conduction mechanisms, whereas in the high electric field range, the hopping conduction and P–F emission were dominant. The specific current fitting process can be found in the literature. ²⁷ Table I, Table II and Table III list the fitted parameters, where ${\varnothing }_{{\rm{t}}}$ is the trap energy level relative to the oxidation film conduction band, a is hopping distance, Ea is activation energy, and R² is a fitting linear correlation parameter.

Table I. TAT fitting parameters.

Electric field	${\varnothing }_{{\boldsymbol{t}}}$	R2
(MV cm−1)	(eV)
6–7.5	1.67	0.99948
7.5–9.5	0.93	0.99999

Table III. Poole-Frenkel current fitting parameters.

Electric field	${\varnothing }_{{\boldsymbol{t}}}$	R2
(MV cm−1)	(eV)
10.5–11	1.53	0.99996

Figures 7–9 show the results of fitting the measured current using the table parameters. The energy band diagrams of the two structures are also shown in Figs. 10–13, where Figs. 10–12 are energy band diagrams of the stacked structures, and Fig. 13 is energy band diagram of the thermal oxidation layer structure. F–N tunneling is the main conduction current of thermally oxidized samples; however, the conduction current mechanism of the stacked structure is more complex. Simultaneously, the location of defects below the SiC conduction band energy level was also verified, and this also corresponded to the bulging shown in Fig. 3b.

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Notably, Frankel–Poole emission is also involved in the breakdown, as observed in the increased current between the electric fields within the range of 10–11 MV cm⁻¹, as shown in the I-V curve of the stacked SiO₂ in Fig. 6. A lower energy band offset might have been presented between the stacked SiO₂ and 4H-SiC compared with that between thermally grown SiO₂ and 4H-SiC, possibly limiting the direct usage of stacked SiO₂ on the 4H-SiC surface. Summarily, the quality of the SiO₂/SiC interface has been significantly improved, and the output characteristics of the device will be enhanced if the stacked SiO₂ structure is applied to the device; moreover, the device threshold voltage may be small. It is a problem that complex conduction mechanisms cause current leakage. Although more complex mechanisms occur in the stacked structure, the device threshold voltage may be comparable to that of the thermal SiO₂ structure.

In this study, a new process of thermal SiO₂ and ALD SiO₂ stacking structures was proposed for the first time and MOS capacitors were prepared. This process effectively reduced the interface state density at the SiO₂/SiC interface compared with the process of thermal oxidation only. This stacked structure may be applicable in actual MOSFET power devices. Moreover, deep energy level traps were found in the stacked structure different from those in the thermal SiO₂ structure. However, more complex conduction current mechanisms were found in the stacked structure compared with the thermal SiO₂ structure. The leakage problem was perhaps the dominant issue for applications of this structure in SiC devices for high-voltage situations. Therefore, future studies should focus on methods to improve gate voltage breakdown characteristics.

This work was supported in part by the Youth Innovation Promotion Association of CAS under Grant Y201926. And we would like to thank Editage (www.editage.cn) for English language editing.