Abstract
III-V RF devices operating at cryogenic temperature are highly desirable for application areas such as space communication or quantum computing. In the case of quantum computation, integration of the readout and control electronics close to the quantum bit (Qubit) stage is needed to allow scaling of the number of Qubits needed for practical applications. Many characteristics of high frequency operation at cryogenic temperature in novel III-V devices are not fully understood. In this study, we will focus on the behaviour of defects at or near the interface between the high dielectric constant (high-k) oxide and InGaAs semiconductor at cryogenic temperature and how it may affect the full device operation at low temperature.
The thermal budget constraints associated with the processing III-V semiconductor devices prohibit the use of high temperature thermal treatments to reduce oxide defect densities in the high-k. This leads to defective oxides presenting higher instability, variability, and degradation issues than in the Si/SiO2 system. The methods developed to investigate defects in the Si/SiO2 metal oxide semiconductor (MOS) system generally attribute the divergence in capacitance voltage (CV) and conductance voltage (GV) from the ideal CV and GV characteristics mostly to interface state defects (ITs) [1], which is not the case of the III-V MOS system. As a consequence, attempts to fit the multi-frequency CV and GV response of III-V MOS structures in the weak inversion regime, using interface states alone, cannot recreate the experimental data.
In this study, we present an advanced MOS defects characterisation method capable of discerning between the contributions of oxide defects (sometimes labelled 'border traps') and ITs. The method relies on the fully physics based simulation of MOS systems, including inelastic tunnelling from the semiconductor to localized defects in the oxide [2] to reproduce the experimental multi-frequency CV and GV characteristics. The simulations include physical models accurately describing the carrier capture/emission processes by oxide traps, and which incorporate tunneling into the dielectric in conjunction with lattice relaxation at the interface/border trap sites [3, 4]. The results will show that the simulations are able to reproduce the room temperature experimental data (both CV and GV) of InGaAs/Al2O3 MOS structures in all bias regions. This new method enables the precise extraction of the density, energy and spatial distribution away from the interface of electrically active oxide defects from different experimental results.
Results will also be presented showing how the multi-frequency CV and GV response of n-InGaAs/Al2O3 and p-InGaAs/Al2O3 MOS structures change with reducing temperature. Measurements at 223K show a marked reduction in the CV and GV dispersion with frequency in the accumulation and depletion regions, consistent with a phonon assisted tunnelling interaction of electrons and holes with defects in the Al2O3. Reduction in the measurement temperature to 10K still demonstrates a residual dispersion of the capacitance and conductance with frequency, which is more marked in the case of the p-InGaAs/Al2O3 MOS structure. The models and trap distributions extracted from room temperature will be applied to the reduced temperature measurements (233 K and 10 K) to investigate the validity of the models and to gain further understanding of defect behaviour and associated device implications at cryogenic temperatures.
[1] E. H. Nicollian and J. R. Brews, "MOS Physics and Technology," John Wiley & Sons, New York, 1982.
[2] A. Palma, et al. Phys. Rev. B Condens. Matter Mater. Phys., 56 (15), pp. 9565-9574 (1997).
[3] E. Caruso, et al. IEEE Trans. Electron Devices, 67 (10), pp. 4372-4378 (2020)
[4] G. Sereni, et al. "IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 705–712, (2015).