Experimental Implementation of Cascaded H-Bridge Multilevel Inverter with an Improved Reliability for Solar PV Applications

Dhanamjayulu, C.; Girijaprasanna, T.

doi:https://doi.org/10.1155/2023/8794874

International Transactions on Electrical Energy Systems

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High-frequency Converters: Design, Control, and Applications

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Research Article | Open Access

Volume 2023 | Article ID 8794874 | https://doi.org/10.1155/2023/8794874

Experimental Implementation of Cascaded H-Bridge Multilevel Inverter with an Improved Reliability for Solar PV Applications

C. Dhanamjayulu¹and T. Girijaprasanna¹

Academic Editor: Murthy Cherukuri

Received18 Aug 2022

Revised04 Jan 2023

Accepted13 Apr 2023

Published28 Apr 2023

Abstract

This study presents the boost converter-based cascaded H-bridge (CHB) multilevel inverter with improved reliability for solar PV (photovoltaic) applications. The solar PV is associated with the boost converter to enhance DC link voltage by using the maximum power point tracking-perturb and observe (MPPT-P & O) technique. The proposed configuration is aimed toward the performance analysis of the boost converter-based CHB MLI by reducing the number of components, low total harmonic distortion (THD), reduced power, less cost function, low total standing voltage (TSV), improved reliability, and switching losses for solar PV application. In this study, a CHB multilevel inverter is used to obtain stepped pure sinusoidal AC from the solar PV array. The proposed boost converter extracts maximum power and enhances higher DC link voltage which provides high efficiency. The boost converter is integrated with a 27-level CHB multilevel inverter to generate near-sinusoidal output voltage with lower THD. The inverter is tested with linear and nonlinear loads for robustness, and during dynamic loads, inverter is stable and well suited to grid-connected applications. A detailed comparison is presented on the component count and reliability aspects with existing MLIs and 27-level MLIs. The simulation outcomes of the implemented arrangement are presented with the help of MATLAB/Simulink, an experimental prototype is developed using a dSPACE RTI1104 controller and also tested in the research laboratory for checking the possibility of the implemented arrangement.

1. Introduction

There must be situated worldwide creativities in favor of the elevation of independent renewable energy schemes. This creativity has run for the growth of renewable power-producing systems that remain accomplished in giving self-sufficient power production with the help of additional standalone renewable energy sources (RES) [1, 2]. The further most usually used hybrid RES is the wind in addition to solar power [3, 4]. These two RES remain irregular; consequently, the utilization of ESS (energy storage system) is typical within stand-governing submissions [5, 6]. The hybrid renewable energy schemes are having some controlling methods which offer a resourceful transfer of power. An approach to the energy translation arrangement as well as converters has various demerits at several stages in the system; this is to be implemented with a lot of technical concentration and investigation in this part [7–9]. Henceforth, there is rapid growth in the study of different RES such as solar, tidal, and wind to extract power. Amongst PV, the energy extracted plays an energetic role, and it is direct current (DC) in nature. After getting DC from panels, it is important to convert as AC to meetup with locals as well as industrial power requirements. For this, the inverters play a very important role [1, 9]. The 2-level MLI are operated underneath, a higher switching frequency, resulting in higher dv/dt of voltage production, higher EMI (electromagnetic interferences) [10, 11] as well as increased heat issues in the switches. The MLI can overawe disadvantages related to the 2-level MLI from multiple points of view. With a created number of MLI levels, an almost unadulterated sinusoidal wave structure is accomplished. As the number of MLI levels rises, the THD in the air conditioner yield is diminished. It can minimize the harmonic contents along with maximizing the power in the AC voltage output side [12, 13]. The tweak game plan serves the purpose of properly turning ON and OFF the force switches. Diode clamped, flying capacitor, and CHB (cascaded H-bridge) MLI are 3 regular MLI topologies [14, 15]. MLIs are usually used in various variable speed drives and renewable energy applications as well as static reactive power compensators [16, 17]. Diode clamped alongside flying capacitor MLI experience issues at higher yield levels such as voltage offsetting alongside unique voltage sharing. Consequently, among the traditional MLI CHB arranging is broadly perceived because of their secluded structure as small as shortcoming open-minded capacity [18–41]. The exchanging heartbeats can be created by utilizing various regulation procedures for MLIs. The boost converter is the standout reasonable converter as it can build the dc voltage as needed, and it is associated with a dc-dc converter among load and sun-based boards to fulfill the necessities [39]. The voltage output from the solar PV feed to the boost converter boosts the output and the output can be changed by changing the parameter of the boost converter.

In this investigation work, a configuration of boost converter-based 27‐level cascaded MLI has been presented as an analysis in detail. A brief description of the boost converter is explained in Section 2. Implemented 27-level cascaded MLI is discussed along with simulation results in Section 3. The proposed system losses, efficiency, TSV, cost function, and reliability are presented in Section 4. The comparison of the proposed system with existing topologies is presented in Section 5. The experimental results are described in Section 6. Finally, the conclusion is discussed in Section 7.

2. Proposed Configuration

Figure 1 shows the projected arrangement, and it involves a solar photovoltaic- (PV)-based boost converter with integrated CHB MLI. The maximum possible voltage at the boost converter to survive high variable input currents from radiation through the photovoltaic array is to be maintained. According to the input voltage variations, the boost converter consisting of switches must be given the gate pulses. For constant voltage, the boost control is provided by the MPPT algorithm.

2.1. Modeling of a Boost Converter

The boost converter circuit contains capacitor (C), inductor (L), diode (D), and a load resistor (R_L) alongside the control switch (S). These components are related to the voltage input source (V_in) to support the voltage. By the obligation cycle control switch, the output voltage of the lift converter is controlled. The output voltage can be differed by shifting the ON season of the switch, and for the obligation cycle (D), the normal yield voltage can be determined by utilizing the following beneath equation:where V_o = output voltage and V_in = input voltage of the converter, respectively, and D = duty cycle.

2.2. Choice of Inductor

The boost converter inductor value is calculated by using following equation:where F_s is the switching frequency (10 kHz) and ΔI_L is the current ripple.

CRF (Current ripple factor) is defined as the ratio between input current ripple and output current. For a respectable estimate of an inductor, the CRF value should be assured within 30%. The inductor current rating is always higher than that of the output maximum current .

2.3. Choice of Capacitor

The value of the capacitor can be obtained fromwhere ΔV₀ = voltage output ripple which is typically measured as 5% of voltage output which produces ΔV₀/V₀ = 5%.

The boost converter modeling can be calculated by using the above equations and the obtained values are presented in Table 1.

2.4. Solar Photovoltaic Powered Boost Converter

The current and voltage received from the solar photovoltaic array depend on temperature, the number of series-connected strings, and the number of parallel-connected string sand irradiance. So, it is essential to select the type of solar panel intelligently. Here, 1STH-215-P panel, 1Soltech with 2 parallel strings along with 2 series-connected modules per string is designated. The specifications of the selected solar panel are given for 1 series-connected module 1 and parallel string at 25°C temperature and irradiance of 1000 W/m² and are described in Table 2. Figure 2 represents the control and operation of a 3-level boost converter 19, which contains two dc-link capacitors C₁ and C₂, boost inductor L, and S₁ and S₂ switches, and Table 1 specifications of the boost converter are tabulated. The 3-level boost converter has 4 modes of operation depending on the switching states. Mode 2 & 3 occurs when either S₁ or S₂ is turned ON. Mode 1 & 4 occurs when S₁ and S₂ are turned OFF or ON, respectively. It is seen that dependent on the estimation of obligation proportion D there are 2 working areas. The converter permits working in Modes 2, 3, and 4 for the obligation cycle (0 < D < 0.85), whereas the converter permits working in Modes 1, 2, and 3 for (0.85 >D < 1). The connection between the complete dc-interface voltage and PV input source voltage is given by the following expression:

2.5. MPPT Method

In favor of tracing the maximum power point, it is required to use an algorithm in the P vs. V graph of the solar photovoltaic module. So, many methods are available to track the maximum power point such as incremental conductance, perturbing, and observing the fractional open-circuit voltage, and genetic algorithm. The MPPT algorithm implemented is represented in Figure 3, and the solar PV panel specifications are mentioned in Table 2.

In this paper, perturb and observe algorithm has been used. By varying the perturbation value, the maximum power point willpower speed can be controlled. Figure 3 shows the P&O algorithm flowchart. The algorithm for perturb and observe technique is as follows:(a)From the solar PV module, read the voltage V_pv and current I_pv values.(b)From the measured I_pv and V_pv, the Power P_pv is calculated.(c)At M^th instant, the value of power and voltage is saved.(d)Repeat step next values at (M + 1)^th instant are measured.(e)From M^th instant, voltage and power at (M + 1)^th instant are detracted with the values.(f)It is inferred that in the correct hand side bend in the force voltage bend of the sun-based PV module where the incline of intensity voltage is negative (dP/dV < 0), and the voltage is practically consistent whereas in the left-hand side, the slant is positive (dP/dV > 0). In this way, the lower obligation cycle is the correct side of the bend and the higher obligation cycle is the left side bend.(g)Contingent upon the sign of dV, for example, (V (M + 1) − V (M)) and dP, for example, (P (M + 1) − P (M)) regardless of whether to build the obligation cycle or to decrease the obligation cycle chooses after deduction of the calculation. Figure 3 shows the flowchart of perturb and observe algorithm. 1Soltech 1STH-215-P solar PV panel generates 60 V dc voltage with 5 A current, and by using a 3-level DC-DC boost converter, it will boost up the voltage 60 to 403 V dc with 4 A, and the simulation and experimental outcomes are shown in Figures 4 and 5, respectively. The simulation results of PV variation for several irradiances are presented in Figure 6, whereas the experimental results of PV irradiance are presented in Figure 7.

The efficiency of the converter during the irradiation condition is calculated as follows.

(a)

(b)

(c)

(a)

(b)

(c)

Equation (5) represents the output power relation of the PV system during irradiation conditions.where I_rr is the irradiance of the PV module , A_m is the module (m²), η_m is the module efficiency = , η_i is the efficiency of the inverter = , and is the converter loss = P_c + P_s.

Hence, during the irradiation of 1000 W/m² to 700 W/m², the efficiency is calculated from (5) and found to be 95.68%.

3. Implementation of CBH 27-Level MLI

The inverter is integrated with a boost converter with solar PV and electric vehicle applications to produce a pure sinusoidal waveform. The boost converter-based cascaded MLI is shown in Figure 8. The presentation of the cascaded MLI is discussed. The single-phase single bridge inverters are associated in a cascaded fashion giving cascaded MLI. In this analysis situs usually from various DC voltage buses, the desired voltage is appreciated. Considering the DC sources, the fell MLIs are considered into 2 kinds, deviated and symmetric inverters. In a symmetric sort, the voltage of the DC joins is held at a similar level.

The inconvenience of symmetric geography is that the expansion in voltage yield levels builds the number of switches. To overcome the above drawback, the DC buses supplied with unequal voltages are named asymmetric topology. The implemented 27-level MLI uses the asymmetric topology as presented in Figure 8. It contains 3 modules with 3 DC buses and each cell contains 4 switches. It is a mix of 3 single-stage H-connect inverters associated with the fell mode. The exchange plan for each single inverter cell is comparable to S₁ = and S₂ = from short-circuiting to avoid the circuit.

The power switches are MOSFETs or IGBTs as shown in Figure 8. The dc voltage is in the proportion of 1 : 3 : 9. A higher no of levels brings about expanded execution with more modest sounds. The benefits of fell staggered inverters are less number of DC sources, exchanging misfortunes, yield exchanging frequencies, decrease in cost, consonant levels, and expanded yield productivity. These wellsprings of DC are connected to a solitary stage H connect inverter, which creates the 3-levels of yield voltages such as follows+V_dc, 0, and −V_dc. The exchanging misfortunes in the framework depend on exchanging recurrence, which thusly is lesser due to the diminished voltage. This examination merges a mix of a few changes to propel the presentation of the inverter. In this technique, the various DC joins are associated with an association of 1 V, 3 V, 9 V… 3S − 1 V. A yield equivalent to 3S voltage levels are created by the inverter. A 27-level MLI is to create 27 distinctive voltage levels in the yield. The 27 levels in the yield waveform are ±13, ±12, ±11, ±10, ±9, ±8, ±7, ±6, ±5, ±4, ±3, ±2, ±1, and 0. By using the above equations, the implemented inverter number of switches and number of levels as well as peak PV output voltage can be attained.

3.1. Modes of Operation of 27-Level Cascaded H-Bridge MLI

For +1 V_dc, the PV output voltage level is +31 v which is generated by turning on switches S₁, S₂, S₆, S₈, S₁₀, and S₁₂ and that can be obtained at the load terminals as shown in Figure 9(a). For +2 V_dc, the PV output voltage level is +62 V which is generated by turning on switches S₃, S₄, S₅, S₆, S₁₀, and S₁₂ and that can be obtained at the load terminals as shown in Figure 9(b). For +3 V_dc, the PV output voltage level is +93 V which is generated by turning on switches S₂, S₄, S₅, S₆, S₁₀, and S₁₂, and that can be obtained at the load terminals as shown in Figure 9(c). For −1 V_dc, the PV output voltage level is −31 V which is generated by turning on switches S₃, S₄, S₆, S₈, S₁₀, and S₁₂ and that can be obtained at the load terminals as shown in Figure 9(d). For −2 V_dc, the output voltage level is −62 V which is generated by turning on switches S₁, S₂, S₇, S₈, S₁₀, and S₁₂ and that can be obtained at the load terminals as shown in Figure 9(e). For −3 V_dc, the output voltage level is −93 V generated with turning on switches S₂, S₄, S₇, S₈, S₁₀, and S₁₂ and that can be obtained at the load terminals as shown in Figure 9(f). Likewise, the remaining levels are followed by using switching (Table 3).

(a)

(b)

(c)

(d)

(e)

(f)

3.2. The Circuit Parameters are Determined for the Proposed 27-Level Topology

The cascaded 27-level inverter parameters such as the number of power switches, sources, voltage levels, and voltage can be estimated as follows.

The number of switches is required as follows:where m = number of basic unit by considering here m value is 3, then

The number of sources is required as follows:

By considering the m value is 3, then

The number of levels is obtained as follows:

By considering the m value is 1, then

The output voltage of the 27-level is determined as follows:

By considering the m value is 3 and V_dc value is 31, then .

The input supplies specified to the circuit are V_dc = 403 V to accomplish the decided pinnacle voltage of 403 V with the loads (R = 100 Ω & 98 mH). The simulation output waveform of the cascaded H-bridge of 27-level MLI is shown in Figure 10. The switching table is shown in Table 3 for the conduction state of switches in 27-level MLI. By using the staircase modulation method, the implemented MLI, gate pulses are created for switches. It is calculated from MATLAB at 10 kHz of switching frequency. The transporter signal is related to a reference sign of 50 Hz. Figure 11 shows the yield voltage just as the current for 27-levels MLI. For the arrangement association, the voltage proportion is 1 : 3 : 9. The information that supplies the predefined voltages to the circuit is V_dc = 31 V, V_1dc = 93 V, and V_3dc = 279 V to accomplish the decided pinnacle voltage of 403 V with the (R = 100 Ω & 98 mH) loads. The yield voltage of recreation yields current alongside THD as introduced in Figures 11 and 12.

4. Calculation of Reliability, TSV, Cost Function, Losses, and Efficiency

4.1. Losses and Efficiency

The misfortunes can be estimated by two methods; two significant misfortunes related to switches are exchanging misfortunes and misfortunes of conductions. The conductivity let-down of IGBTs can be overcome [20, 21].where V_IGBT is the drop in forwarding voltage of the IGBT, and the drop in forwarding voltage of the diodes is V_d. R_IGBT is the equivalent resistance of the IGBTs, and the equivalent resistance of the diodes is R_d, and β is a constant with IGBT specification favors. The normal estimation of the MLIs conductive force misfortune (Q_cl) can be given as follows [20, 21] as N_d diodes and N_IGBT transistors are present in the current path at a time t [20, 21].

Because of the energy the exchanging misfortunes can be assessed used during turn-off and turn-on cycles in the switches, it is esteemed dependent on straight contrasts of the exchanging voltage and current [20, 21]. The energy value could be as follows:where Em_off and Em_on are the turn-on and turn-off misfortunes with l. The misfortunes from exchanging are comparable to the amount of the misfortunes from turn-off and turn-on energy, esteemed as follows:

The total loss of power was valued as follows:

The inverter efficiency is given as follows:where P_in and P_out correspond to the input and output power.

The power output can be assessed in the following way:

The experimental power output of 718.7 W for twenty-seven-level inverters is obtained using (14) (V_rms = 282.84 V and I_rms = 2.828 A). The parameter values for calculation are collected from the IGBT CM7FDU datasheet. From the performance characteristics plot the R_IGBT is 0.4 and V_switch value (0.6 V) is taken, 200 ns turn-off delay, 100 ns turn-off, 250 ns turn-off, and 12 switches turn-off as 300 ns. The proposed inverter design will cover 53 steps in one complete cycle [20, 21]. The losses from the conduction are calculated using equation (9).

Q_cl = 58.75 W and Em_off and Em_on are calculated from equations (13) and (14). Em_off = 0.254 W and Em_on = 0.127 W.

The switching losses are designed as follows:

Q_sl = 0.381 W, total losses are designed using (16) during switching and lead time.

The ɳ (efficiency) is designed by utilizing equation (17):

The above calculations guarantee the proposed 27-inverter efficiency at 92.38 percent.

4.2. Total Standing Voltage (TSV)

The standing voltage of the inverter is estimated using the following equations:

In open-circuit conditions, the switches will block the voltages of blocking voltages of switches [37];

Blocking voltages across the switches are as follows:

The total voltage blocked across the switches as follows:

4.3. Cost Function (CF)

The cost function of the inverter is estimated using the following equation [37].where the N_sw is the switches count, α is the weighting coefficient, and V_switch is the voltage across the switch.

The inverter estimated cost function is tabulated in Table 4.

4.4. Reliability Calculation of the Inverter

The mean time to failure rate (MFFT) is important for the inverters; the reliability analysis is presented for the proposed system. The total MTTF of power electronic circuits can be calculated by estimating the total failure rate (FR) value of the circuit elements that are present [38]. The total FR and λ_T, are calculated by multiplying the number of components, such as switches and diodes by their corresponding FR values.

The total MTTF of the power electronic circuit can be derived from following equation:

The MTTFT of the electronic circuits can be calculated based on the number of device counts.

The inverter has 12 switches (N_SW) and 12 diodes, respectively, and the total failure rate (FR) and mean time to failure rate (MFFT) are estimated using (26) and (27).

5. Comparative Analysis

A boost converter-based CHB staggered inverter is proposed for the utilization of extracted PV energy. The solar photovoltaic is connected to the boost converter, and it enhanced voltage from PV output voltage 60 V to 403 V with the help of the MPPT technique. The boosted output voltage is higher compared to existing converters [22–25] as shown in Table 5 and Figure 13 shows the comparison of the proposed converter with existing converters. The output of the implemented 27-level CBH multilevel inverter has fewer switching losses as well as switch count compared with the existing topologies [26–30] as shown in Table 6 and comparison is shown in Figure 14. As experimental voltage value adapts to disorient situations of injected voltage and power. The inverter which is a linked PV module can be a unit with reduced power losses as it consists of fewer driver circuits. This study reports a 27-level inverter using just helped voltage got from a sustainable power source. The inverter proficiency is high and the yield voltage waveform is entirely sinusoidal. The expense is little as the number of intensity switches used is 12. The power switches are reduced apparently due to a reduced number of power driver circuits, also low transmission losses than traditional inverter modules. Expanding the degree of the inverter can get a few points of interest: get a decent voltage wave structure and very low THD 3.77% which is achieved through the experiment as shown in Figure 15. The comparison of implemented inverter THD values with existing topologies. The conventional MLIs are compared with 27MLI is tabulated in Table 7 and Figure 16 shows the comparison of implemented MLI with the conventional MLIs. The reliability analysis conducted for the inverter with existing MLIs is shown in Table 8. The inverter has reliability when compared to existing MLIs in all aspects as shown in Figure 17. The references [26, 27, 29] have less THD compared with the proposed MLI but the MBV of the other topologies are high whereas the MBV of the proposed topology is less, which results in the added advantage of the topology.

6. Experimental Results

The extracted PV two voltages and one programmable DC source are fed to the 27 MLI. The 27-level MLI equipment model setup was used in the model scale and tried tentatively. The social occasion of Simulink block bunches into dSPACE RTI 1104 computerized input/output ports are performed, and the flight of stairs tweaks PWM technique execution in MATLAB/Simulink is performed. To rearrange continuous interfacing applications, by the computerized I/O ports, the 20 yield pins are controlled. From the dSPACE RTI1104, the TLP 250 driver is separated to include, is the beat made. The experimental twenty-seven output waveform is shown in Figure 18(a). The consistent state testing checks with R-load with 400 V alongside the current yield are accomplished with 4 A. Yield current and voltage RMS esteems were to start with 282.84 V and 2.828 A, correspondingly. The staging point between the heap current and the heap voltage is zero, as appeared in the waveform. Consistent state testing with an R-load, competition after here gave the L-load 403 V and 3.4 A, correspondingly, and relating RMS esteems were achieved with 284.96 V and 2.404 A, correspondingly. The output voltage and currents are 403 V and 2.3 A, and the RMS values are 284.96 V and 1.626 A, correspondingly obtained investigational results are given in Figures 18(b)–18(d). The investigational results check at consistent state, load aggravation conditions, executed with R to L load as appeared in Figure 19, executed with L to R load as appeared in Figure 20, correspondingly. In assurance, stacks infrequently happen particularly and they will surely occur in a blend of resistive and inductive burdens. Generally, in a particular spot, when an R (resistive) load is by and by working an unexpected collection of L (inductive)-load corresponding to the R load or the other way around is indistinguishable likely. Figure 21 shows the experimental results of the 27‐level multilevel inverter THD trial voltage is 4.02%. The proposed system hardware setup is shown in Figure 22. The experimental output parameters are shown in Tables 9 and 10.

(a)

(b)

(c)

(d)

The actualized inverter created a higher number of voltage yield levels with a less number of equipment components and low THD values. Similar aftereffects of the trial have appeared in Tables 9 and 10. The experimental setup component details are mentioned in Table 11.

7. Conclusion

In this study, a boost converter-based CHB staggered inverter for solar PV applications is implemented. Solar PV is associated with the lift converter and improved voltage from PV yield voltage 60 V to 403 V with the help of the MPPT method. The inverter is integrated with a boost converter with solar PV applications to generate a pure sinusoidal waveform. A 27-level CHBMLI is implemented with reduced power losses and lower THD. The 27-level topology has been planned and afterward reenacted in MATLAB/Simulink, and it uses 12 switches and three voltage sources to develop 27-level voltage sources THD for 27 levels is 3.77% and efficiency is 92.38%. The inverter has lower TSV, is cost-effective, and has improved reliability. Finally, a detailed comparison with the existing system is given focusing on the advantages of the proposed converter and implementation for the 27-level inverter. The proposed topology is limited to medium-power devices with a restricted number of levels. The proposed system is well suited for electric vehicles and grid-connected applications and FACTs [8].

Data Availability

The data used to support the findings of this study are included in the article.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

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Copyright © 2023 C. Dhanamjayulu and T. Girijaprasanna. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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