The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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A Study on Circuit Design Method for Linearity and Range Improvement of CMOS Analog Current-Mode Multiplier

CMOS 아날로그 전류모드 곱셈기의 선형성과 동적범위 향상을 위한 회로설계 기법에 관한 연구

  • 이대니얼주헌 (서울과학기술대학교 IT융합공학과) ;
  • 김형민 (서울과학기술대학교 정보통신미디어공학전공) ;
  • 박소연 (서울과학기술대학교 미디어IT공학과) ;
  • 노태민 (서울과학기술대학교 미디어IT공학과) ;
  • 김성권 (서울과학기술대학교 전자IT미디어공학과)
  • Received : 2020.02.26
  • Accepted : 2020.06.15
  • Published : 2020.06.30
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Abstract

In this paper, we present a design method for improving the linearity and dynamic range of the analog current mode multiplier circuit, which is one of the key devices in an analog current mode AI processor. The proposed circuit consists of 4 quadrant translinear loops made up of NMOS transistors only, which minimizes physical mismatches of the transistors. The proposed circuit can be implemented at 117㎛ × 109㎛ in 0.35㎛ CMOS process and has a total harmonic distortion of 0.3%. The proposed analog current mode multiplier is expected to be useful as the core circuit of a current mode AI processor.

이 논문에서는 아날로그 전류모드 인공지능 프로세서에서 핵심 디바이스 중에 하나인 아날로그 전류 모드 곱셈기 회로의 선형성과 동적범위 향상을 위한 설계 기법을 소개한다. 제안하는 회로는 4 quadrant Translinear loop를 NMOS 트랜지스터만으로 구성하여, 트랜지스터의 물리적 Mismatch를 최소화하는 설계로 0.35㎛ CMOS 공정에서 117㎛ × 109㎛로 구현가능하였으며, 최대 전고조파왜율 0.3% 의 선형성을 확보할 수 있었다. 제안한 아날로그 전류모드 곱셈기는 전류모드 인공지능 프로세서의 핵심 회로로 유용할 것으로 기대된다.

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References

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