skip to main content
research-article

To lock, swap, or elide: on the interplay of hardware transactional memory and lock-free indexing

Published:01 July 2015Publication History
Skip Abstract Section

Abstract

The release of hardware transactional memory (HTM) in commodity CPUs has major implications on the design and implementation of main-memory databases, especially on the architecture of high-performance lock-free indexing methods at the core of several of these systems. This paper studies the interplay of HTM and lock-free indexing methods. First, we evaluate whether HTM will obviate the need for crafty lock-free index designs by integrating it in a traditional B-tree architecture. HTM performs well for simple data sets with small fixed-length keys and payloads, but its benefits disappear for more complex scenarios (e.g., larger variable-length keys and payloads), making it unattractive as a general solution for achieving high performance. Second, we explore fundamental differences between HTM-based and lock-free B-tree designs. While lock-freedom entails design complexity and extra mechanism, it has performance advantages in several scenarios, especially high-contention cases where readers proceed uncontested (whereas HTM aborts readers). Finally, we explore the use of HTM as a method to simplify lock-free design. We find that using HTM to implement a multi-word compare-and-swap greatly reduces lock-free programming complexity at the cost of only a 10-15% performance degradation. Our study uses two state-of-the-art index implementations: a memory-optimized B-tree extended with HTM to provide multi-threaded concurrency and the Bw-tree lock-free B-tree used in several Microsoft production environments.

References

  1. M. Abadi, T. Harris, and M. Mehrara. Transactional Memory with Strong Atomicity Using Off-the-shelf Memory Protection Hardware. In PPoPP, pages 185--196, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. J. H. Anderson and M. Moir. Universal Constructions for Multi-Object Operations. In PODC, pages 184--193, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. C. Blundell, E. C. Lewis, and M. M. Martin. Subtleties of Transactional Memory Atomicity Semantics. IEEE Comput. Archit. Lett., 5(2):--, Feb 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. I. Calciu et al. NUMA-Aware Reader-Writer Locks. In PPoPP, pages 157--166, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. I. Calciu et al. Invyswell: A Hybrid Transactional Memory for Haswell's Restricted Transactional Memory. In PACT, pages 187--200, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. J. Chung et al. ASF: AMD64 extension for lock-free data structures and transactional memory. In MICRO, pages 39--50, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. cpp-btree. https://code.google.com/p/cpp-btree/.Google ScholarGoogle Scholar
  8. T. Crain, E. Kanellou, and M. Raynal. STM Systems: Enforcing Strong Isolation Between Transactions and Non-transactional Code. In ICA3PP, pages 317--331, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. P. Damron et al. Hybrid Transactional Memory. In ASPLOS, pages 336--346, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. C. Diaconu et al. Hekaton: SQL Server's Memory-Optimized OLTP Engine. In SIGMOD, pages 1243--1254, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. D. Dice et al. Applications of the Adaptive Transactional Memory Test Platform. In TRANSACT Workshop, 2008.Google ScholarGoogle Scholar
  12. Azure DocumentDB. https://www.documentdb.com.Google ScholarGoogle Scholar
  13. G. Graefe. A Survey of B-tree Locking Techniques. ACM Trans. Database Syst., 35(3):16:1--16:26, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. J. Gray et al. Quickly Generating Billion-record Synthetic Databases. In SIGMOD, pages 243--252, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. S. Harizopoulos et al. OLTP Through the Looking Glass, and What We Found There. In SIGMOD, pages 981--992, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. T. L. Harris et al. A Practical Multi-Word Compare-and-Swap Operation. In Distributed Computing, pages 265--279. 2002. Google ScholarGoogle ScholarCross RefCross Ref
  17. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In ISCA, pages 289--300, 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Intel. Intel 64 and IA-32 Architectures Optimization Reference Manual, September 2014.Google ScholarGoogle Scholar
  19. A. Israeli and L. Rappoport. Disjoint-Access-Parallel Implementations of Strong Shared Memory Primitives. In PODC, pages 151--160, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. C. Jacobi et al. Transactional Memory Architecture and Implementation for IBM System z. In MICRO, pages 25--36, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. T. Karnagel et al. Improving In-Memory Database Index Performance with Intel Transactional Synchronization Extensions. In HPCA, pages 476--487, 2014.Google ScholarGoogle Scholar
  22. P. L. Lehman and S. B. Yao. Efficient Locking for Concurrent Operations on B-Trees. TODS, 6(4):650--670, 1981. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. V. Leis et al. The Adaptive Radix Tree: ARTful Indexing for Main-memory Databases. In ICDE, pages 38--49, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. V. Leis et al. Exploiting Hardware Transactional Memory in Main-Memory Databases. In ICDE, pages 580--591, 2014.Google ScholarGoogle ScholarCross RefCross Ref
  25. Y. Lev, M. Moir, and D. Nussbaum. PhTM: Phased transactional memory. In Transact, 2007.Google ScholarGoogle Scholar
  26. J. Levandoski et al. High Performance Transactions in Deuteronomy. In CIDR, 2015.Google ScholarGoogle Scholar
  27. J. Levandoski, D. B. Lomet, and S. Sengupta. The Bw-Tree: A B-tree for New Hardware Platforms. In ICDE, pages 302--313, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. D. B. Lomet. Process Structuring, Synchronization, and Recovery Using Atomic Actions. In Proceedings of the ACM Conference on Language Design for Reliable Software, pages 128--137, 1977. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Y. Mao, E. Kohler, and R. T. Morris. Cache Craftiness for Fast Multicore Key-Value Storage. In EuroSys, pages 183--196, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. The Story Behind MemSQLs Skiplist Indexes. http://blog.memsql.com/the-story-behind-memsqls-skiplist-indexes/.Google ScholarGoogle Scholar
  31. C. C. Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees. In ISCA, pages 69--80, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. I. Pandis, P. Tözün, R. Johnson, and A. Ailamaki. PLP: Page Latch-free Shared-everything OLTP. PVLDB, 4(10):610--621, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In MICRO, pages 294--305, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. J. Sewall et al. PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors. PVLDB, 4(11):795--806, 2011.Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. N. Shavit and D. Toutitou. Software Transactional Memory. In PODC, pages 204--213, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. V. Srinivasan and M. J. Carey. Performance of B+ Tree Concurrency Algorithms. VLDB Journal, 2(4):361--406, 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. R. M. Yoo et al. Performance Evaluation of Intel Transactional Synchronization Extensions for High-Performance Computing. In SC, pages 19--29, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. To lock, swap, or elide: on the interplay of hardware transactional memory and lock-free indexing

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image Proceedings of the VLDB Endowment
        Proceedings of the VLDB Endowment  Volume 8, Issue 11
        July 2015
        264 pages
        ISSN:2150-8097
        Issue’s Table of Contents

        Publisher

        VLDB Endowment

        Publication History

        • Published: 1 July 2015
        Published in pvldb Volume 8, Issue 11

        Qualifiers

        • research-article

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader