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III–V compound semiconductor transistors—from planar to nanowire structures

  • New Materials for Post-Si Computing
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Abstract

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications.

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Acknowledgments

The work at IBM Research—Zurich has been supported by the European Union 7th Framework Programs Steeper (grant agreement no. 257267) and E2SWITCH (grant agreement no. 619509). The work at Lund University has been supported by the Swedish Research Council, the Swedish Foundation for Strategic Research, and the European Union 7th Framework Program E2SWITCH (grant agreement no. 619509). Research at the National Taiwan University on high κ /III–V interfaces and III–V MOSFETs has been supported by the Ministry of Science and Technology (grant numbers NSC 102–2622-E-002–014 and NSC 102–2112-M-002–022-MY3), Ministry of Education, Taiwan, TSMC Corporation, and AOARD/US Air Force. Research at MIT on III–V MOSFETs has been supported by FCRP-MSD, Intel Corporation, ARL, SRC, NSF (award no. 0939514) and Sematech.

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Authors and Affiliations

  1. Materials Integration and Nanoscale Devices, IBM Research, Switzerland

    Heike Riel

  2. Lund University, Sweden

    Lars-Erik Wernersson

  3. Department of Physics and Graduate Institute of Applied Physics, National Taiwan University, Taiwan

    Minghwei Hong

  4. Microsystems Technology Laboratories, Massachusetts Institute of Technology, USA

    Jesús A. del Alamo

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  1. Heike Riel
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Correspondence to Heike Riel.

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Riel, H., Wernersson, LE., Hong, M. et al. III–V compound semiconductor transistors—from planar to nanowire structures. MRS Bulletin 39, 668–677 (2014). https://doi.org/10.1557/mrs.2014.137

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