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From planar to vertical nanowires field-effect transistors

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Abstract

The authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/Ioff ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104 but with poor dynamics which can be explained by the high interface traps density.

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Authors and Affiliations

  1. Laboratoire des Technologies de la Microélectronique (LTM)–UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054, Grenoble, France

    Guillaume Rosaz, Bassem Salem, Priyanka Periwal, Alexis Potié, Thierry Baron, L. Latu-Romain & S. David

  2. CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054, Grenoble, France

    Guillaume Rosaz, Nicolas Pauc & Pascal Gentile

Authors
  1. Guillaume Rosaz
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  2. Bassem Salem
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  3. Nicolas Pauc
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  4. Pascal Gentile
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  5. Priyanka Periwal
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  6. Alexis Potié
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  7. Thierry Baron
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  8. L. Latu-Romain
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  9. S. David
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Rosaz, G., Salem, B., Pauc, N. et al. From planar to vertical nanowires field-effect transistors. MRS Online Proceedings Library 1439, 101–107 (2012). https://doi.org/10.1557/opl.2012.1422

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  • DOI: https://doi.org/10.1557/opl.2012.1422

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