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Aggressively Scaled P-Channel Mosfets With Stacked Nitride-Oxide-Nitride, N/O/N, Gate Dielectrics

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Abstract

Ultrathin (tox, eq < 2.0 nm) Si3N4/SiO2(hereafter N/O) gate dielectrics with improved interface characteristics compared to devices with thermal oxides have been formed by remote plasma enhanced CVD of Si3N4onto oxides. If the Si-Si02 interface is intentionally nitrided prior to the Si3N4deposition, the increased physical thickness of the N/O stack combined with the interfacial nitridation reduces the direct tunneling current by more than two orders of magnitude. The ensuing device structure can then be characterized as N/O/N. The top nitride layer is also an effective boron diffusion barrier improving short channel characteristics in p+-poly PMOSFETs. In addition, nitrogen can also be transported to the silicon/dielectric interface during post-deposition RTAs, and this reduces degradation of transconductance during hot carrier stressing.

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Wu, Y., Lucovsky, G. Aggressively Scaled P-Channel Mosfets With Stacked Nitride-Oxide-Nitride, N/O/N, Gate Dielectrics. MRS Online Proceedings Library 567, 101–106 (1999). https://doi.org/10.1557/PROC-567-101

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  • DOI: https://doi.org/10.1557/PROC-567-101

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