Fabrication of Three-Dimensional MIS Nano-Capacitor Based on Nanoimprinted Single Crystal Silicon Nanowire Arrays

Y.      Zhai; M.      Palard; L.      Mathew; Muhammad   M.   Hussain; C.   G.   Willson; E.      Tutuc; S.   K.   Banerjee

doi:10.2174/1876402911204040333

Abstract

We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications.

Keywords: Capacitor, DRAM, Nano-Imprint, Nanowire, vapor-liquid-solid, lithography, EOT, FinFETs, Si etching, Bosch process cycles, atomic layer deposition, TEM micrographs, Si-nanowires, planar structure, UV nano-imprint lithography