Abstract
This work proposed a transition sensitive finite state machine – TSFSM
using the novel master-slave transition detector for low-power or
high-speed applications. To solve the problems of hazard-free
requirements and difficult synthesis of the exisiting locally clock
finite state machine, TSFSM uses multi-bit XOR gate as the input burst
detector and the local clock generator. The measured results show that
the proposed implementation reduce the difficulty of its design and
synthesis, and it also reduces the the area and power consumption by
about 86% and 18.2%.