doiSerbia

Effects of pulsed negative bias temperature stressing in p-channel power VDMOSFETs

Manić Ivica (Faculty of Electronic Engineering, Niš)
Danković Danijel (Faculty of Electronic Engineering, Niš)
Davidović Vojkan (Faculty of Electronic Engineering, Niš)
Prijić Aneta (Faculty of Electronic Engineering, Niš)
Đorić-Veljković Snežana (Faculty of Civil Engineering and Architecture, Niš)
Golubović Snežana (Faculty of Electronic Engineering, Niš)
Prijić Zoran (Faculty of Electronic Engineering, Niš)
Stojadinović Ninoslav (Faculty of Electronic Engineering, Niš)

Our recent research of the effects of pulsed bias NBT stressing in p-channel power VDMOSFETs is reviewed in this paper. The reduced degradation normally observed under the pulsed stress bias conditions is discussed in terms of the dynamic recovery effects, which are further assessed by varying the duty cycle ratio and frequency of the pulsed stress voltage. The results are analyzed in terms of the effects on device lifetime as well. A tendency of stress induced degradation to decrease with lowering the duty cycle and/or increasing the frequency of the pulsed stress voltage, which leads to the increase in device lifetime, is explained in terms of enhanced dynamic recovery effects.

Keywords: VDMOSFET, NBTI, pulsed bias stress, threshold voltage, lifetime

Projekat Ministarstva nauke Republike Srbije, br. OI-171026 i br. TR-32026