Facta universitatis - series: Electronics and Energetics 2014 Volume 27, Issue 2, Pages: 251-258
https://doi.org/10.2298/FUEE1402251C
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Cited by
CMOS IC radiation hardening by design
Camplani Alessandra (INFN-Milano and Department of Physics, Università degli Studi di Milano Via G. Celoria, Milano, Italy)
Shojaii Seyedruhollah (INFN-Milano and Department of Physics, Università degli Studi di Milano Via G. Celoria, Milano, Italy)
Shrimali Hitesh (INFN-Milano and Department of Physics, Università degli Studi di Milano Via G. Celoria, Milano, Italy)
Stabile Alberto (INFN-Milano and Department of Physics, Università degli Studi di Milano Via G. Celoria, Milano, Italy)
Liberali Valentino (INFN-Milano and Department of Physics, Università degli Studi di Milano Via G. Celoria, Milano, Italy)
Design techniques for radiation hardening of integrated circuits in
commercial CMOS technologies are presented. Circuits designed with the
proposed approaches are more tolerant to both total dose and to single event
effects. The main drawback of the techniques for radiation hardening by
design is the increase of silicon area, compared with a conventional design.
Keywords: radiation hardening, CMOS technology, integrated circuits