Abstract
Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.
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Original Russian Text © Vandna Sikarwar, Saurabh Khandelwal, Shyam Akashe, 2013, published in Izv. Vyssh. Uchebn. Zaved., Radioelektron., 2013, Vol. 56, No. 9, pp. 13–23.
The Endeavour in this paper was supported by ITM University (Gwalior, India) with the collaboration of Cadence System Design (Bangalore, India).
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Sikarwar, V., Khandelwal, S. & Akashe, S. Analysis and design of low power SRAM cell using independent gate FinFET. Radioelectron.Commun.Syst. 56, 434–440 (2013). https://doi.org/10.3103/S0735272713090021
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DOI: https://doi.org/10.3103/S0735272713090021