Abstract
In this paper we have proposed a FinFET based 6T static random access memory (SRAM) cell. FinFET devices can be used to improve the performance, reduce the leakage current and power dissipation. The purpose of this article is to reduce the leakage current and leakage power of FinFET based 6T SRAM cell using various techniques in 45 nm technology. FinFET based 6T SRAM cell has been designed and analysis has been carried out for leakage current and leakage power. For low power memory design the most important problem is to minimize the sub-threshold leakage current and gate leakage current. This work introduces a technique based on threshold voltage, gate oxide thickness and power supply setting together to minimize sub-threshold and gate leakage current of 6T SRAM cell. These simulation results are carried out using Cadence Virtuoso Tool at 45 nm technology.
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Original Russian Text © R.S. Kushwah, V. Sikarwar, 2015, published in Izv. Vyssh. Uchebn. Zaved., Radioelektron., 2015, Vol. 58, No. 7, pp. 26–39.
ORCID: 0000-0001-5229-0204
This work was supported by ITM University (Gwalior) in collaboration with Cadence System Design (Bangalore, India).
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Kushwah, R.S., Sikarwar, V. Analysis of leakage current and power reduction techniques in FinFET based SRAM cell. Radioelectron.Commun.Syst. 58, 312–321 (2015). https://doi.org/10.3103/S0735272715070031
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DOI: https://doi.org/10.3103/S0735272715070031