Design and Implementation of Multi-Channel Readout Circuits for Low-Temperature Environments

Abstract

Infrared sensors and focal plane imaging arrays are among the most important types of devices in the field of aerospace applications. To effectively amplify the small signals collected by infrared sensors and focal plane imaging arrays for subsequent processing, a new multi-channel preamplifier circuit based on ultra-low temperatures was designed in this study to read the acquisition signals of such devices. The technology of an SMIC 180 nm CMOS with 1.8 V power was adopted to realize the circuit. Meanwhile, an eight-level adjustable gain switch was used to increase the selectivity of signal processing. According to the simulation’s results, the single-channel power consumption of the circuit in the 77 K ultra-low temperature environment was only 5.17 mW. The circuit could drive a large load of 200–400 pF with an open-loop gain of 131.4 dB, which showed excellent performance in driving large loads, providing high gain and consuming less power. Additionally, the circuit exhibited good aspects for front-end signal reading and processing of infrared sensors and focal plane arrays in extreme environments.

1. Introduction

In the past few decades, with the continuous exploration of outer space by humans [1,2], more and more signal processing equipment has been applied to aerospace equipment [3,4,5]. Infrared sensors and focal plane imaging arrays are one type of such device [6,7,8,9]. With the development of semiconductor technology, the scenarios where these devices are applied have become increasingly widespread. Currently, more detectors can be integrated into a focal plane (FPC) system as pixel units for imaging [10,11,12]. Analog-to-digital conversion and digital processing units, output buffers, multiplexers, preamplifiers, detector arrays, and optical lenses should be included in a complete infrared detector [13]. Among the biggest challenges for this type of device is the level of power consumption and the signal processing capabilities.

Due to the low-temperature operating environment, there are stringent requirements in terms of both power consumption and performance. A two-stage RC-coupled amplification circuit [14,15,16,17,18,19,20,21,22,23] has typically been applied in traditional preamplifier circuits, while a window comparator [24] can be used to discriminate the amplified signals. Common preamplifiers consist of two stages of amplification using operational amplifiers and a window comparator [25]. This circuit has high gain and can amplify proper signals to an appropriate level [26,27], but it cannot effectively suppress the influence of common-mode noise on the output signal [28,29]. The device itself is not suitable for low-power circuits, as it consumes a large amount of power [30,31]. In addition, it is greatly affected by temperature, and its application in environments with an ultra-low temperature is limited, making it difficult to achieve good detection and stability. At the same time, common-mode noise is also affected [32,33,34,35,36,37]. To overcome the disadvantages of traditional amplifiers’ performance, this work aimed to develop a signal amplifier circuit with low power, high gain, and low noise.

A low-power front-end signal amplifier was developed based on a P-differential amplifier in this work. The amplifier consisted of a bias circuit, a first-stage input amplifier circuit, a second-stage amplifier circuit, a resistor network, and a gain selection circuit. It was suitable for processing signals in environments with ultra-low temperatures. Compared with the input signal, which undergoes integration and conversion processing, the photoelectric current signal generated by the photodiode was relatively small. Therefore, a low-power design strategy was adopted to design a folded common-source and common-gate two-stage amplifier, which had high gain and low noise performance while significantly reducing power consumption.

The outline of this article is as follows. The conventional two-stage amplifier cell and proposed amplifier cell are described in Section 2, Section 3 illustrates and discusses the simulation and analyses of various cells, and Section 4 concludes this work.

2. An Adjustable Gain Amplifier Based on a Low-Temperature Environment

As the signals to be collected by infrared sensors and focal plane imaging arrays are relatively small, amplifying and processing these signals effectively through an amplifier is an important application scenario for such devices. An ideal operational amplifier has the following characteristics: an infinite input impedance and output current; infinite conversion rate and open-loop gain; no noise, offset, power waste, or signal distortion; and no limitations on the load, frequency, and power supply voltage. However, in practical designs, the parameters of operational amplifiers are interdependent, and the performance of an op-amp is often designed according to the actual requirements.

2.1. Traditional Circuit Design Theory and Implementation

The main structure of a traditional two-stage operational amplifier consists of two single-stage amplifiers, as shown in Figure 1, including a folded cascade differential input stage and a common-source gain output stage, with auxiliary circuits, such as bias and frequency compensation circuits. The differential input stage uses a folded cascade structure input pair. In Figure 1, VDD is the voltage of the power supply, GND is the ground, INn and INp are the differential input signals, Mi is the corresponding MOS transistor, vbi [1, 4] is the corresponding bias signal, CL is the capacitor, and OUT is the output.

Figure 2 shows the equivalent small-signal circuit model of the traditional two-stage amplifier, which ignores the effect of modulating the channel’s length, the body effects, and parasitic circuit capacitance other than the Miller capacitance and load capacitance.

In Figure 2, Vin is the input signal; gmi is the transconductance; Cin, C1, C2, Cc and CL are the equivalent capacitance; and Req and RL are the equivalent resistance in the small-signal model.

This operational amplifier is divided into two stages: the cascade stage is used to increase the DC gain, and the common-source amplifier is used to improve the overall gain. The amplifier’s gain is the product of the first-stage gain and the second-stage gain, and the overall gain of the amplifier is calculated by Equation (1), where A represents the total gain of the two-stage amplifier; A₁ and A₂ represent the gain of the first- and second-stage amplifiers; R_o1 and R_o2 represent the total equivalent resistance of each stage of the amplifier; g_m1 and g_m2 represent the transconductance of the two stages; and r_o1, r_o10, r_o9, r_o12, and r_o13 represent the equivalent resistance of the equivalent small-signal model of the second-stage amplifier.

$$A=A_1{A}_2=G_{m1}{R}_{O1}{G}_{m2}{R}_{O2}=g_{m1}{g}_{m2}((r_{o1}+r_{o10})//r_{o9})(r_{o12}+r_{o13})$$

(1)

Traditional operational amplifiers meet the requirements of most signal-processing applications with a low-input impedance and moderate bandwidth. However, due to the low working temperature of the circuit designed in this study, high bandwidth, high gain, high speed, and high linearity were required, resulting in traditional amplifiers being unable to meet these requirements.

2.2. The Architecture of the Amplifier Circuit in this Study

In Figure 3, CTRL is the control signal; Bias Circuit is the bias circuit module; two-stage amplifier is the structure of the two-stage amplifier; INn and INp are the differential input signals; N and Y are the output signals of CTRL through the inverter; N is the opposite to the output signal of CTRL; and Y is the same as the output signal.

To meet the requirements of a low working temperature, high bandwidth, high gain, high speed, and high linearity, this study designed an amplifier for specific application scenarios and improved its performance to a certain extent. It included a bias circuit and a second-stage amplifier circuit. The bias circuit provided the bias current signal. At the same time, the second-stage amplifier consisted of a PMOS differential input stage, a folded cascade circuit, a transconductance linearization circuit, and an output stage circuit.

2.2.1. Input Stage Circuit

Due to the small input signal voltage of the front stage, a PMOS differential pair was used as the input stage, which consisted of a folded cascade input stage and a Class AB-controlled output stage that provided bias for the output of the n-type and p-type transistors and a voltage difference, allowing the two transistors to operate synchronously, pulling up and pushing down together. The input stage used only PMOS differential input, resulting in low noise, lower common-mode voltage as input, and effective elimination of the effects of the substrate. Figure 4 shows the input stage circuit of the amplifier, where INn and INp are the input differential signals; Mi [0, 10] is the code for a different CMOS; bi [1, 4] is a different bias signal; and VDD and GND are the 1.8 V power supply and the ground.

2.2.2. Output Stage Circuit

Figure 5 shows a schematic diagram of the output stage circuit of the operational amplifier, which consisted of a folded cascade and a Class AB-controlled output stage, a zeroing resistor, and a Miller capacitor. The zeroing resistor could further weaken the Miller effect, and the two-form RC Miller compensation. Miller capacitors and zero-adjustment resistors have been included in this design. Through an increase in the zero-adjustment resistor, the unit-gain bandwidth of the amplification circuit could be expanded. Adjusting the value of Miller capacitors also ensured that the circuit had the same phase margin, thereby ensuring the stability of the circuit. Under the regulation of the Miller capacitance, the amplifier operated stably and had a large open-loop gain. However, its unit-gain bandwidth was small, which introduced a right half-plane zero point, thereby reducing the stability of the operational amplifier’s frequency response. Therefore, by adding zero resistance to the amplifier, the unit-gain bandwidth was expanded by offsetting the secondary poles without changing the other parameters, Thus, the position of the zero point was adjusted. Since we set the minimum gain to two, a PMOS differential pair was used as the input. The output stage’s transistors were M17 and M18, which were controlled by M15, and M16 in Class AB and M11 and M14. In Figure 5, Mi [3, 18] represents the different CMOS codes, VDD and GND represent the 1.8 V power and ground, C1 and C2 represent the Miller capacitors, R1 and R2 represent the zero-adjustment resistors, and out represents the output.

From the formulae, it can be inferred that provided the threshold is well-matched, two pairs of transconductance linear loops consisting of M11, M12, M15, M17, and M13, and M14, M16, and M18 can accurately control the static current of the output transistor, thus reducing the power consumption. The gate voltage supplies of these transistors satisfied the following formulas, where V_GS is the voltage of the gate-source of the MOSFETs. W represents the channel width of the MOS transistor, and L represents the channel length of the MOS transistor.

$$\left|v_{GS11}\right|+\left|v_{GS12}\right|=\left|v_{GS15}\right|+\left|v_{GS17}\right|$$

(2)

$$v_{GS13}+v_{GS14}=v_{GS16}+v_{GS18}$$

(3)

$$I_1=\frac{{\left(\frac{W}{L}\right)}_{17}}{{\left(\frac{W}{L}\right)}_{11}}{I}_{11}$$

(4)

$$I_1=\frac{{\left(\frac{W}{L}\right)}_{18}}{{\left(\frac{W}{L}\right)}_{14}}{I}_{14}$$

(5)

When the current sources are equal, the static current of the output transistors is

$$I_{out}=\frac{{\left(\frac{W}{L}\right)}_{17}}{{\left(\frac{W}{L}\right)}_{11}}{I}_{11}=\frac{{\left(\frac{W}{L}\right)}_{18}}{{\left(\frac{W}{L}\right)}_{14}}{I}_{14}$$

(6)

With reasonable settings for the static currents I₁₁ and I₁₄ and the W/L of M11 and M14, the output transistors M17 and M18 can operate in the weak inversion region in a static state, reducing the static power consumption. When an AC signal arrived, due to the high AC impedance of the floating current source, M17 and M18 were driven to the strong inversion region by the AC signal, providing a dynamic current ten times that of the static current, achieving the characteristics of Class ab. The static operating point of the output stage could be stabilized through the analysis above, so it was not affected by the common mode input signal.

2.3. The 16-Channel Programmable Gain Amplifier Array

The signal readout and processing circuit consisted of 16 channels, with input signals (IN), reference signals (REF), and differential output signals (OUT1 and OUT2); each channel could be controlled and adjusted separately. Figure 6 shows the overall architecture of the signal processing circuit, which is mainly composed of an amplification circuit, a programmable gain section, and a bias circuit. Each channel contains multiple identical preamplifiers, and the gain of the programmable channel ranges from 2 to 16. Each channel contains two operational amplifiers (OAs) and a programmable resistor network for switching different gains. The output channel can drive large capacitance loads of 200–400 pF, and the bias current (RBAIS) uses an external reference current source. The chip was designed using SMIC 180 nm CMOS technology. In Figure 6, IN is the input signal, REF is the reference signal, and OUT1 and OUT2 are the output signals.

When a fixed value of gain is needed to meet the design’s requirements, an appropriate operational amplifier should be selected according to the requirements. In this study, a series-connected ladder resistor network was used to achieve programmable gain, and the amplification factor was determined by the resistor network. In addition, this structure can be combined with external operational amplifiers and resistors to form a classic three-ampere meter amplifier and different channels can be selected to work according to the actual needs. The amplifier’s nodes were connected to the TG transmission gate to determine the circuit’s gain. The transmission gate had relatively low resistance, so the switch’s resistance did not affect the circuit. There were eight adjustable gain levels in total in this design, with N + 1 resistors in the step ladder. Formula (1) describes the relationship between the circuit’s gain and the resistance value under normal circumstances. The three gain control ports’ gain on the outermost side of the channel [2:0] controlled the MOS switch of the resistor array by outputting eight control signals through a 3–8 decoder. Two operational amplifiers were located at both ends of the resistor array, utilizing the virtual short characteristics of the two input ports of the operational amplifier to transfer the difference in the voltage between the input signal and the reference voltage to the resistor array. As long as any MOS switch was turned on, the resistor array generated a certain amount of current. The total resistance of the resistors turned on by different MOS switches was different. The larger the total resistance value of the resistors turned on, the smaller the current formed in the resistor array. The current flowed through the entire resistor array, forming an output voltage, so the smaller the current, the smaller the output voltage. Thus, by inputting different control signals through the gain port, the on and off state of different MOS switches could be changed, thereby controlling the output gain. Gain [n] represents the values of gain under different factors of amplification, and Ri represents the corresponding resistance in the resistance network.

$$Gain\left[n\right]=\frac{{\displaystyle \sum _{i=1}^n{R}_i}}{{\displaystyle \sum _{i=n+1}^{N+1}{R}_i}}+1$$

(7)

2.4. Architecture of the Layout

The layout system is shown in Figure 7. The IC design’s functionality was designed and verified using Cadence Virtuoso and Spectre tools. All simulations were performed under various process settings (AVDD = 1.8 V and a processing temperature of 77 K in a cryogenic environment), and the performance was verified at 77 K.

3. Results of the Complete Simulation of the Operational Amplifiers and Channels

3.1. Performance of the Operational Amplifier

3.1.1. DC Characteristics

The working current of the operational amplifier during stable operation often determines the static power consumption of the amplifier. This design verified the typical static current of the operational amplifier at 77 K, which was only 2.87 mA. Therefore, the static power consumption of a single operational amplifier was only 5.17 mW. This was mainly due to the optimization of the output current of the power transistor, which greatly optimized the static power consumption of the amplifier. This was beneficial for greatly increasing the working efficiency of the device under conditions of limited power.

Table 1. The static current of the operational amplifier.

Parameter	Min	Mean	Max
Quiescent current (mA)	2.42	2.87	2.96

shows the magnitude of static current under different processes.

This study had a typical current value of 2.87 mA under a large load capacitance of 200 pF, while in [19], the current reached 2.22 mA under 100 pF. With an increase in the load, the current in this study improved by nearly 0.55 mA, thus making it more advantageous in terms of power consumption.

3.1.2. AC Characteristics

Figure 8 shows the open-loop AC frequency response of the operational amplifier at 77 K, with a load capacitance of 200 pF. The unit gain bandwidth (UGBW) is 70 MHz, the phase margin is 57.55°, and the gain is 131.14 dB.

The frequency of the phase and gain of the amplifier from 77–330 K were analyzed, and the results of the simulation are shown in Figure 9. From the results of the simulation, it can be seen that the overall trend of the phase and unit-gain bandwidth changed with a consistent temperature.

Table 2. DC gain, unit-gain bandwidth (UGBW), and phase margin (PM) of the amplifier; load = 200 pF at 77 K.

Parameter	Min	Mean	Max
Gain (dB)	130.50	131.14	130.67
PM (degrees)	49.00	57.55	62.68
UGBW (MHz)	60.25	70.00	70.61

presents the performance of the simulation in terms of gain, PM, and UGBW under different processes at a temperature of 77 K.

Table 2 compared with the results of [19], the parameters were optimized to some extent under typical testing conditions, especially the DC gain and UGBW. The typical values in the literature are 96 dB and 35 MHz, while in this study, they were 131.14 dB and 70.00 MHz.

The power supply rejection ratio (PSRR) is a measure of the ability of a circuit to suppress any variations in the power supply from being passed to its output signal. Typically, the typical value of PSRR is 80 dB. Figure 10 shows the PSRR of the operational amplifier with a capacitance load of 200 pF and a temperature of 77 K. The PSRR of the operational amplifier was as high as 94.28 dB, indicating its excellent ability to suppress the power supply’s noise.

Table 3. Results of the simulated PSRR under different processing parameters at temperature a of 77 K with a load of 200 pF.

Parameter	Min	Mean	Max
PSRR (dB)	90.86	94.28	94.74

Simulated PSRR simulation results under different Process corners.

The common-mode rejection ratio (CMRR) is one of the parameters used to measure the ability of a differential amplifier (also known as a difference amplifier) to suppress the input’s common-mode signals in analog circuits. It is an important parameter for evaluating the suppression of common-mode noise in data acquisition hardware products. Typically, the typical value of CMRR is 70 dB or more. Figure 11 shows the common-mode rejection ratio of the operational amplifier with a capacitor load of 200 pF and a temperature of 77 K. Due to the use of a folded common-source common-gate structure and a large-sized input transistor, and the biasing in the sub-threshold region, the mismatch of the input transistor was reduced. The common-mode rejection ratio of this operational amplifier was as high as 114.54 dB.

Table 4. Results of the simulated CMRR results for different processing parameters with a load of 200 pF.

Parameter	Min	Mean	Max
CMRR (dB)	106.91	114.54	116.82

simulates the CMRR simulation results under different Process corners.

Noise is one of the most important parameters in the design of a preamplifier, as it determines the performance of the amplifier and also determines the minimum amplitude of the test signal in the circuit. It also determines the dynamic input range and output common-mode range. The noise of operational amplifiers mainly consists of three parts: operating amplifier voltage noise, operational amplifier current noise, and the thermal noise generated by feedback resistors. In this design, good noise performance was achieved while maintaining low power consumption. The operational amplifier was simulated under a unity-gain configuration, and the test results are shown in

Table 5. Input-referred noise of the operational amplifier.

Parameter	Integrated (1 Hz to 500 kHz) (µVrms)	Spot Noise (f = 10 kHz) (nV/√Hz)
Unity gain	67.32	36.87

. The main sources of noise were the M10 and M9 MOS transistors in the amplifier, which, together, accounted for about 80% of the total noise.

Table 6. The step response results of the operational amplifier under conditions of 77 K, with a typical conversion rate of 28.39 V/µs, as shown in the graph.

Parameter	Min	Mean	Max
Slew rate (V/μs)	21.62	28.39	29.67

simulates the simulation results of SR under different Process corners, and the typical value is 28.39 V/μs.

The following Figure 12 shows the simulation results of large signal step response.

Figure 13 shows the Monte-Carlo simulation results of the main parameters of the amplifier designed in this article.

The following

Table 7. Comparison of the performance of the proposed amplifier and the existing methods.

Specifications	This Work	[19]	[20]	[21]
Technology	0.18 μm	0.18 μm	0.18 μm	0.5 μm
Supply voltage (V)	1.8 V	1.8 V	1.8 V	+1 V/−1 V
Loading capacitance (pF)	200	100	200	70
Compensation	Miller	Miller	Load cap	Load cap
SR (V/μs)	28.39	51.00	74.10	13.2
DC gain (dB)	131.14	98.00	72.00	76.80
Phase margin (°)	57.55	71.00	50.00	75.1
UGBW (MHz)	70.00	21.00	86.50	3.4
Input-referred noise (uV/√Hz)	0.0369 at 10 kHZ	0.25 at 100 kHz	–	0.023 at 1 MHz
Power dissipation (mW)	5.17	3.00	11.9	0.1

shows the comparison between the amplifier designed in this article and other amplifiers.

3.2. Amplifier Channel Testing

3.2.1. Channel Noise

Noise plays a significant role in the performance of the amplifier in the front-end amplifier, and the size of the input-referred noise is also one of the most important design indicators in the channel.

Table 8. Input-referred noise of the channels.

Gain	Integrated (1 Hz to 500 kHz) (µVrms)	Spot Noise (f = 10 kHz) (nV/√Hz)
2	3.34	8.90
4	3.69	9.85
8	4.01	10.69
16	4.22	11.25

shows the simulated reference noise at different gains. The input noise was simulated under four gain conditions, and as the gain continued to increase, the channels’ input noise also increased.

3.2.2. Bandwidth and Gain of the Channels

The single channel in this design was set with eight adjustable gain levels for amplifying the differential output signal of the channel. Figure 14 shows the simulated sine wave signal with an input amplitude of 10 mV and a frequency of 100 kHz applied to the input under a temperature of 77 K. The input’s common-mode voltage was VDD/2 with a magnitude of 0.9 V. The differential output signals of the channel were measured at different gains. In Figure 14, it can be observed that under the maximum amplification factor of sixteen, the differential voltage of 10 mV was amplified to 160 mV, and under the maximum amplification factor of two, the voltage was successfully amplified to 20 mV, meeting the design requirements.

3.2.3. Cutoff Frequency of Channels with Different Gain Settings

The cutoff frequency of a channel is the boundary of the frequency range of the signals transmitted through the channel, beyond which the signals will be attenuated or filtered out. In this design, the cutoff frequency of the channel was adjusted by changing the gain of the channel. Figure 15 shows the cutoff frequencies of the channels at different gain settings at 77 K. The maximum cutoff frequency was above 4 MHz. This has a positive significance for us for collecting signals at higher frequencies.

3.2.4. Post-Layout Simulation of the Channels

We simulated the gain under different factors of amplification, and compared the results with the previous post-layout simulations. The gain matched the amplification factor. We simulated the amplification performance of the channel, and the results of the simulation are shown in Figure 16. During the process of amplification by 2–16×, the gain varied by 6–24.1 dB, which met the design goal.

4. Conclusions

A signal readout circuit for infrared sensors and focal plane arrays in low-temperature environments was proposed in this article. The circuit features 16 selectable channels and an eight-level adjustable gain design and was designed using the SMIC 0.18-micron CMOS process. The circuit uses a two-stage folding cascade transconductance linear ring structure with PMOS input, and an output terminal with zero-pole adjustment was added by zeroing the resistor and the Miller capacitor. According to the results of the simulation, the amplifier had a gain of up to 131.4 dB, a phase margin of 57.55°, a unit-gain bandwidth of 70 MHz, and a controlled Class AB output stage structure that can drive a large load capacitance (200–400 pF) while consuming only 5.17 mW of power. A Monte Carlo simulation was also run on the main parameters of the amplifier, and good results were achieved. Finally, the performance of the eight-level output was tested for the single-channel, with a differential input signal of 10 mV. Structural analysis was conducted on the output end, and favorable signal amplification results were obtained. We also conducted post-layout simulation on the gain of Channel 8, and the simulation results met the design requirements. The successful design of this circuit provides a high-performance front-end signal readout and a processing solution for infrared sensors and focal plane arrays in low-temperature environments.