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Hardware Transactional Memories: A Survey

Hardware Transactional Memories: A Survey

Arsalan Shahid, Maryam Murad, Muhammad Yasir Qadri, Nadia N. Qadri, Jameel Ahmed
Copyright: © 2016 |Pages: 19
ISBN13: 9781522502876|ISBN10: 1522502874|EISBN13: 9781522502883
DOI: 10.4018/978-1-5225-0287-6.ch003
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MLA

Shahid, Arsalan, et al. "Hardware Transactional Memories: A Survey." Innovative Research and Applications in Next-Generation High Performance Computing, edited by Qusay F. Hassan, IGI Global, 2016, pp. 47-65. https://doi.org/10.4018/978-1-5225-0287-6.ch003

APA

Shahid, A., Murad, M., Qadri, M. Y., Qadri, N. N., & Ahmed, J. (2016). Hardware Transactional Memories: A Survey. In Q. Hassan (Ed.), Innovative Research and Applications in Next-Generation High Performance Computing (pp. 47-65). IGI Global. https://doi.org/10.4018/978-1-5225-0287-6.ch003

Chicago

Shahid, Arsalan, et al. "Hardware Transactional Memories: A Survey." In Innovative Research and Applications in Next-Generation High Performance Computing, edited by Qusay F. Hassan, 47-65. Hershey, PA: IGI Global, 2016. https://doi.org/10.4018/978-1-5225-0287-6.ch003

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Abstract

The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mutual exclusion. Possession of one or more locks protects access to shared data. But, due to some flaws they become a suboptimal solution. The idea of transactional memory is in research presently as an alternative to locks. Among which, one way is hardware transactional memory. Atomicity is well supported by using transactions in hardware. In this chapter, we have focused on hardware transactional memories and the work done on them so far.

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