Stress Test of Cascode Switch Using SiC Static Induction Transistor

Takashi Matsumoto; Yasunori Tanaka; Koji Yano

doi:10.4028/www.scientific.net/MSF.1004.985

Paper Titles

A Subcircuit SPICE Model for SiC Charge-Balance Schottky Diodes
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Temperature Dependence of the Bipolar Activation and the Leakage Currents of 10 kV 4H-SiC JBS-Diodes
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Analysis of Barrier Inhomogeneities of P-Type Al/4H-SiC Schottky Barrier Diodes
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Power Cycling Capability and Lifetime Estimation of Discrete Silicon Carbide Power Devices
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Stress Test of Cascode Switch Using SiC Static Induction Transistor
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Accelerated Testing of SiC Power Devices under High-Field Operating Conditions
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Investigations on the Resistance Reduction Effect of Double-Trench SiC MOSFETs under Repetitive Avalanche Stress
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High-Temperature Reliability Analysis of 1200V/100A 4H-SiC Junction Barrier Schottky Diodes
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Evaluation of SiC-MOSFET by Repetitive UIS Tests for Solid State Circuit Breaker
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HomeMaterials Science ForumMaterials Science Forum Vol. 1004Stress Test of Cascode Switch Using SiC Static...

Stress Test of Cascode Switch Using SiC Static Induction Transistor

Abstract:

Stress tests were conducted for the cascode switch using the SiC buried gate static induction transistor (SiC-BGSIT). The stress of the reverse overshoot voltage was periodically applied to the pn junction between the gate terminal and source one in the BGSIT in the cascode with pulses of 40kHz for 202 hours. This simulates the stress which can be occurred in the channel region of the BGSIT during the turn-off and turn-on operation with a parasitic inductance in the interconnection of the cascode package. The result of the stress tests has revealed that there is no significant difference between the electrical characteristics of the BGSIT cascode sample before the stress and those after the stress. Thus, the BGSIT cascode can guarantee high reliability against the stress. The result from the drain current DLTS suggests that no deferent kind of defect is created in the channel region of the BGSIT by the stress.

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Periodical:

Materials Science Forum (Volume 1004)

Pages:

985-991

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.1004.985

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Online since:

July 2020

Authors:

Takashi Matsumoto, Yasunori Tanaka, Koji Yano*

Keywords:

Cascode, DLTS, JFET, SiC, SIT, Wide Bandgap (WBG)

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* - Corresponding Author

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