Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures

Masato Noborio; Jun Suda; Tsunenobu Kimoto

doi:10.4028/www.scientific.net/MSF.600-603.679

Paper Titles

Model Calculation of SiC Oxidation Rates in the Thin Oxide Regime
p.663

Oxygen-Partial-Pressure Dependence of SiC Oxidation Rate Studied by In Situ Spectroscopic Ellipsometry
p.667

TEM Observation of SiO₂/4H-SiC Hetero Interface
p.671

Influence of Metallization Annealing on Channel Mobility in 4H-SiC MOSFET on Carbon Face
p.675

Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO₂ Stack Gate Structures
p.679

Anomalously High Channel Mobility in SiC-MOSFETs with Al₂O₃/SiO_x/SiC Gate Structure
p.683

Scattering Mechanisms in Silicon Carbide MOSFETs with Gate Oxides Fabricated Using Sodium Enhanced Oxidation Technique
p.687

High Channel Mobility of MOSFET Fabricated on 4H-SiC (11-20) Face Using Wet Annealing
p.691

High Channel Mobility of 4H-SiC MOSFET Fabricated on Macro-Stepped Surface
p.695

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Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO₂ Stack Gate Structures

Abstract:

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.