Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress

Gerald Rescher; Gregor Pobegen; Tibor Grasser

doi:10.4028/www.scientific.net/MSF.858.481

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HomeMaterials Science ForumMaterials Science Forum Vol. 858Threshold Voltage Instabilities of Present...

Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress

Abstract:

We study the threshold voltage (V_th) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the V_th causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed V_thinstabilities are likely a fundamental physical property of the SiC-SiO₂system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.

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Periodical:

Materials Science Forum (Volume 858)

Pages:

481-484

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.858.481

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Online since:

May 2016

Authors:

Gerald Rescher*, Gregor Pobegen, Tibor Grasser

Keywords:

4H-SiC, BTI, Electron Trapping, MOSFET, PbS, PBTS, Threshold Voltage Drift

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