Published November 9, 2012 | Version v1
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Vhdl Implementation of A Mips-32 Pipeline Processor

Creators

  • 1. Surya World Institutions of Academic Excellence
  • 2. Sachdeva Engineering College for Girls

Description

This paper presents the design and implement a basic five stage pipelined MIPS-32 CPU. Particular attention will be paid to the reduction of clock cycles for lower instruction latency as well as taking advantage of high-speed components in an attempt to reach a clock speed of at least 100 MHz. The final results allowed the CPU to be run at over 200 MHz with a very reasonable chip area of around 900,000nm2.

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References

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