An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

Shiv Bhushan; Santunu Sarangi; Gopi Krishna S.; Abirmoya Santra; Sarvesh Dubey; Pramod Kumar Tiwari

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대한전자공학회
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 학술저널
Journal of Semiconductor Technology and Science Vol.13 No.4
2013.8 367 - 380 (14page)

저자정보

Shiv Bhushan (National Institute of Technology)
Santunu Sarangi (National Institute of Technology)
Gopi Krishna S. (National Institute of Technology)
Abirmoya Santra (National Institute of Technology)
Sarvesh Dubey (IIT(BHU))

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In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium (Si1-x Gex) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from tow-dimensional (2D) potential distribution of channel region. The (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson"s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si1-x Gex layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLASTM, a 2D device simulator from Silvaco Inc.

#Double-material-gate(DMG) #hot carrier effect(HCE) #drain induced barrier lowering(DIBL) #strained-silicon(s-Si) on silicon-germanium (Si< #SUB> #1-x< #/SUB> # Ge< #SUB> #x< #/SUB> #) MOSFETs