Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory

Jaewon Cha; Keewon Cho; Seunggeon Yu; Sungho Kang

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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 학술저널
Journal of Semiconductor Technology and Science Vol.17 No.1
2017.2 147 - 155 (9page)

저자정보

Jaewon Cha (Yonsei University)
Keewon Cho (Yonsei University)
Seunggeon Yu (SK Hynix)
Sungho Kang (Yonsei University)

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A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudorandom pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more lowcost testing solutions compared to the previous pseudo-random testing patterns.

#NAND flash-memory #reliability testing #quasi-random generation