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Abstract
Ⅰ. INTRODUCTION
Ⅱ. SIMULATION METHODOLOGY
Ⅲ. RESULTS AND DISCUSSION
Ⅳ. CONCLUSION
REFERENCES
H. Mertens et al., “Vertically stacked gate-allaround Si nanowire transistors : key process optimizations and ring oscillator demonstration,” in IEDM Tech. Dig., Dec. 2017, pp. 828-831.
J. Zhang et al., “High-k Metal Gate Fundamental Learning and Multi-VT Options for Stacked Nanosheet Gate-All-Around Transistor,” in IEDM Tech. Dig., Dec. 2017, pp. 537-540.
S. Barraud et al., “Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain,” in IEDM Tech. Dig., June 2017, pp. 464-647.
M. A. Elmessary et al., “Study of Strained Effects in Nanoscale GAA Nanowire FETs Using 3D Monte Carlo Simulations,” in ESSDERC, Sep. 2017, pp. 184-187.
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