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Abstract
Ⅰ. INTRODUCTION
Ⅱ. DEVICE FABRICATION
Ⅲ. MEMORY DEVICE CHARACTERIZATION
Ⅳ. CONCLUSIONS
REFERENCES
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X. He, et al, “Implementation of fully self-aligned homojunction double-gate a-IGZO TFTs,” IEEE Electron Device Lett., Vol. 35, No. 9, pp. 927-929, Sep. 2014.
S. Y. Lee, “Improvement on the stability of amorphous indium gallium zinc oxide thin film transistors using amorphous oxide multilayer source/drain electrodes,” Trans. Elect. Electron. Mater., Vol. 17, No. 6, pp. 143-145, Jun. 2016.
S. H. Nam, et al, “NOT and NOR logic circuits using passivation dielectric involved dual gate in a- InGaZnO TFTs,” IEEE Electron Device Lett., Vol. 34, No. 12, pp. 1527-1529, Dec. 2013.
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