Demonstration of 1200 V/1.4 mΩ cm² vertical GaN planar MOSFET fabricated by an all ion implantation process

To evaluate the pn-junction breakdown voltage, we fabricated a pn-diode by ion implantation. Figure 1 schematically depicts the fabricated pn-diode. The n-type GaN (0001) substrate was obtained by hydride vapor phase epitaxy. Then a 10 μm thick n-GaN layer was epitaxially grown by metal organic chemical vapor deposition (MOCVD) on the substrate. The net donor concentration of the n-GaN epitaxial layer was around 1.5 × 10¹⁶ cm⁻³. Mg ions were selectively implanted on the n-GaN layer. The Mg ions were implanted with 10–240 keV and a total dose of 8.4 × 10¹³ cm⁻² to obtain a 0.3 μm thick box-profile of 1 × 10¹⁸ cm⁻³ with a p+ contact layer of 2 × 10¹⁹ cm⁻³ near the surface. After Mg ion implantation, N ion implantation was carried out sequentially. N ions were implanted with 10–180 keV and a total dose of 9.9 × 10¹³ cm⁻². In addition, samples without N sequential implantation were fabricated.

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After Mg and N implantation, the wafers were annealed at 1300 °C for 5 min in a N₂ atmosphere at standard pressure with an AlN encapsulation cap to prevent GaN dissociation. After annealing, the AlN cap was chemically removed. AFM measurements in a 1 μm square area indicated that the typical root-mean-square surface roughness of GaN after activation annealing was 0.25 nm.

A plasma-CVD apparatus with TEOS gas deposited a 400 nm thick SiO₂ layer for the field insulating film at 350 °C. The anode was composed of nickel and gold, while the cathode was composed of titanium and aluminum.

Figure 2 shows the depth profile of the Mg concentration analyzed by SIMS for each sample before and after activation annealing. The Mg profile before annealing between the Mg implanted layer and the Mg and N sequential implanted layer were the same. However, the Mg profile after annealing differed slightly at a depth of about 100 nm.

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Figure 3 schematically depicts the fabricated vertical GaN planar MOSFETs by the all ion implantation process. A short cell pitch design of 5 μm with an i-line stepper was used to reduce the channel resistance. The designed size of the active region on the photomask was 91 μm × 40 μm. The designed channel length (L_ch) was 1 μm. The junction FET (JFET) length (L_JFET) was 1 μm, and the source length (L_c) was 2 μm. In consideration of the current spread in the drift layer, the area of the active region used to calculate the on-resistance was set to 101 μm × 50 μm by adding the drift layer thickness (10 μm) to the designed size of the active region assuming a 45° model.²⁵⁾

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We adopted a single-layer electrode structure to avoid the complicated process of stacked electrodes [Fig. 3(a)]. The source parasitic resistance of a single-layer electrode structure was large compared to the stacked electrode in vertical contact with the source implanted region because the source electrode of a single-layer electrode structure is in contact with the active region at a position besides the horizontal direction. The sheet resistance in the source implanted region was about 100 Ω sq⁻¹, and 18 source implanted regions measuring 2 μm width and 40 μm length were connected in parallel in the active region. Considering the horizontal current flow, the estimated source parasitic resistance was 1.4 mΩ cm². Since the source parasitic resistance was considered to be very large relative to the on-resistance of the vertical GaN MOSFET, the source parasitic resistance must be measured and subtracted from the on-resistance to evaluate the effective on-resistance of the active region.

The n-type GaN (0001) substrate was obtained by the acidic ammonothermal method. Then a 10 μm thick n-GaN layer was epitaxially grown by MOCVD on the substrate. The net donor concentration of the n-GaN epitaxial layer was around 1 × 10¹⁶ cm⁻³.

Firstly, Mg ions were selectively implanted on the n-GaN layer. Mg ions were implanted with 10 to 700 keV with a total dose of 6.5 × 10¹³ cm⁻². Afterwards, N ions were implanted sequentially with 10–600 keV and a total dose of 6.7 × 10¹³ cm⁻². Secondly, Si ions were selectively implanted into the source regions with 15–40 keV and a total dose of 1.9 × 10¹⁵ cm⁻². Thirdly, O ions were selectively implanted into the JFET region with 10 to 700 keV and a total dose of 2.3 × 10¹³ cm⁻² to reduce the JFET resistance.

After the triple ion implantation, the wafers were annealed at 1300 °C for 5 min in a N₂ atmosphere at standard pressure with AlN encapsulation cap. Finally, the AlN cap was chemically removed.

Then a plasma-CVD apparatus with TEOS gas deposited a 100 nm thick SiO₂ layer at 300 °C. Titanium and aluminum were used as the gate, source, and drain metal, while nickel was used as the body contact metal. Forming gas annealing was performed at 400 °C for 30 min.

Figure 4 shows the depth profiles of the Mg and Si concentrations in the source implanted region, and Fig. 5 shows the depth profile of the O concentration of the JFET region after activation annealing. All concentrations were analyzed by SIMS measurements. The Mg concentration near the surface was adjusted to control the threshold voltage (V_th) to about 3 V.²⁰⁾ Additionally, increasing the Mg concentration in the deep region provided a sufficiently thick p-well region. Furthermore, the O ions were implanted into the JFET region deeper than the Mg were implanted into the p-well region. Under these conditions, the donor concentration in the JFET region was 1.2 × 10¹⁷ cm⁻³ and the activation efficiency of O atoms was about 30%. It has been reported that O substitutes for N and forms a 29 meV shallow donor level into epitaxially grown GaN. This shallow donor level is slightly deeper than the 17 meV donor level formed by substituting Ga with Si.²⁶⁾ Furthermore, other studies have reported donor activation by O ion implantation, but they have a poor activation efficiency (<5%).^27–29) It is assumed that the defects formed by O implantation were not significantly recovered because their activation heat treatment temperature was 1200 °C or less. On the other hand, a relatively high activation efficiency of 30% was obtained. Thus, the donor concentration in the JFET region could be increased since our activation temperature was 1300 °C.

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Figure 6 shows the reverse I–V characteristics of the pn-diode fabricated by ion implantation. The diameter of the ion implantation region is 100 μm. Subsequent N ion implantation drastically suppresses the leakage current and increases the breakdown voltage. The I–V characteristics of the N-ion-implanted samples show discontinuous points. However, the discontinuous points are attributed to limitations of the measurement system and not the actual I–V characteristics of the device because all three devices show discontinuities in a similar current–voltage range.

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Figure 7 plots the breakdown voltage as a function of the net donor concentration. The breakdown voltage improves by the N sequential implantation at any donor concentration. Several studies have found that the N sequential implantation effectively reduces the N vacancies.^30,31) Using CV measurements, PL, and positron annihilation spectroscopy, we reported that N sequential implantation reduces hole traps due to N vacancies.²²⁾ Therefore, the breakdown voltage improves due to the enhanced pn junction characteristics. Unfortunately, the forward characteristics of the fabricated pn-diodes and/or electrical properties of the Mg implanted layer itself have not yet to be evaluated since the p-type contact is not sufficiently improved and ohmic contact is not obtained. Consequently, evaluating the activation ratio of the Mg implanted layer is a future task.

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Figure 8 shows the I_d–V_d output characteristics on fabricated GaN MOSFETs. The fabricated MOSFETs show normal MOS channel behaviors such as a suitable drain current control by the gate voltage, good ohmic contact, and a low gate leakage current (<1.0 × 10⁻³ A cm⁻²). The on-resistance determined from the slope of the I_d–V_d curve at V_g = 30 V and V_d = 1 V is 2.78 mΩ cm².

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Figure 9 shows the I_d–V_g transfer characteristics of the simultaneously formed lateral GaN MOSFETs on the Mg implanted region. The effects of the parasitic resistance must be eliminated to evaluate the MOS channel property. Hence, the long channel MOSFETs with a 100 μm channel length (L_ch) and a 100 μm gate width (W_g) were fabricated. The V_th was determined as the gate bias intercept from the linear extrapolation of I_d based on the current equation of linear region,³²⁾

$$\begin{eqnarray}&&{I}_{{\rm{d}}}=\displaystyle \frac{{W}_{{\rm{g}}}}{{L}_{{\rm{ch}}}}{\mu }_{{\rm{FE}}}{C}_{{\rm{ox}}}\left({V}_{{\rm{g}}}-{V}_{{\rm{th}}}\right){V}_{{\rm{d}}}\end{eqnarray} \tag{ 1 }$$

which corresponds to the strong inversion point. Here, μ_fe is the field effect mobility and C_ox is the gate oxide capacitance. The V_th is 2.5 V, and the peak of μ_fe is 159 cm² V⁻¹ s⁻¹. V_th extracted from the transfer characteristics of the vertical MOSFET is also 2.5 V, suggesting that the device geometry does not significantly degrade the channel.

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Figure 10 shows the breakdown measurement of the fabricated GaN vertical MOSFET. The breakdown voltage was measured while applying −5 V to the gate electrode. The fabricated GaN vertical MOSFET breaks down around 1200 V. The drain leakage current at 1000 V is less than 1.0 × 10⁻³ A cm⁻². Therefore, the all ion implantation process can realize a vertical GaN planar MOSFET with a high breakdown voltage of 1200 V and a low on-resistance of 2.78 mΩ cm².

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We evaluated each on-resistance component in the vertical MOSFET using the simultaneously formed test structures to obtain an information for further reduction of the on-resistance. The main resistance components of the fabricated vertical GaN planar MOSFET are attributed to the drift layer resistance, JFET resistance, channel resistance, and source parasitic resistance. The calculated on-resistance of the substrate is 0.27 mΩ cm² from the specific resistance of 6.7 mΩ cm and thickness of about 400 μm. However, the substrate resistance should be reduced to 1/10 or less because the substrate is sufficiently thick relative to the active region and the current spreads in the substrate. Therefore, the substrate resistance is negligible.

Firstly, we evaluated the resistance of the test structure where Si was implanted into all surface regions of the vertical MOSFET. The calculated resistance of this structure, which consists of the JFET resistance and the drift layer resistance due to the negligible MOS-region and source access resistances, is 1.02 mΩ cm². According to the previous report,²⁾ the maximum electron mobility in a high-quality n-GaN drift layer grown on a GaN free-standing substrate is 930 cm² V⁻¹ s⁻¹ at a Si concentration of 8 × 10¹⁵ cm⁻³. Considering the current spread from the narrow JFET area with a width of 1 μm to the drift layer, the estimated resistance of JFET and the drift layer with an electron mobility of 930 cm² V⁻¹ s⁻¹, carrier density of drift layer of 1 × 10¹⁶ cm⁻³, thickness of 10 μm, and carrier density of JFET region of 1 × 10¹⁷ cm⁻³ is 1.05 mΩ cm². This calculated value agrees well with the measured one. In addition, the resistance of this test structure without O ion implantation is 3.01 mΩ cm², confirming that O ion implantation significantly reduces the JFET resistance.

Secondly, the channel resistance was calculated from the resistance of vertical MOSFETs with different channel lengths, a large JFET length and a large cell pitch of 8 μm. In such devices, the difference in the resistance corresponds to the difference in the channel resistance because the drift layer resistance and source parasitic resistance are the same while the JFET resistance is negligible due to the large JFET length of 3 μm. By converting the channel resistance obtained from these devices with a cell pitch of 8 μm into a cell pitch of 5 μm, the channel resistance is 0.38 mΩ cm². On the other hand, the sheet channel resistance of simultaneously formed lateral GaN MOSFETs is about 7700 Ω sq⁻¹. Furthermore, in the active region of the vertical GaN planar MOSFET, 38 MOS channel regions with a 40 μm width and 1 μm length are connected in parallel. Therefore, the channel resistance assumed from the sheet resistance is 0.26 mΩ cm². The slight difference between the two calculation methods is attributed to the difference between the designed and actual channel length.

The remaining resistance of 1.38 mΩ cm² is the source parasitic resistance caused by the source electrode being in contact with the active region in the horizontal direction. This value agrees well with the expected source parasitic resistance of 1.4 mΩ cm² calculated from the source sheet resistance. This parasitic resistance can be reduced by applying a stacked electrode in vertical contact with the source implanted region.

Therefore, the effective on-resistance of the active region excluding the source parasitic resistance is 1.4 mΩ cm².