A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor

Masaharu Kobayashi

doi:10.7567/APEX.11.110101

1. Introduction

In today's highly information-oriented society, the cyber physical system (CPS) has been an important business platform. Tremendous amounts of data are collected from real space. These data are stored and analyzed in cloud computing in virtual space. Then, new strategic social services are provided back to the real space. In CPS, an Internet-of-Things (IoT) edge device plays an important role as a sensor node device. The number of IoT devices will grow to be trillions or more; thus, the power consumption of an IoT device must be ultralow because of power constraints. From the economical viewpoint, battery maintenance and replacement for each IoT device will cost a lot. Therefore, ultimately, an IoT device should operate by generating and managing its own power with the use of energy harvesting techniques. The available power supply depends on the environment. For example, in a room environment, the available power may be as much as 1 µW from human vibration, environmental radio, and so on.¹⁾ However, a modern commercially available sensor node device consumes tens or hundreds of µW. Therefore, to realize an autonomous IoT device, power consumption should be reduced by more than tenfold from current levels. This challenge is addressed by introducing new integrated device technologies.

To illustrate the device technology that will be needed, first, the power consumption of a low-power microcontroller unit (MCU) is estimated. Figure 1 shows the power consumption of MCU versus the active rate, which represents the switching times of a transistor per second on average for different technologies and leakage currents. In this model, dynamic and static powers were calculated on the basis of commercial low-power MCUs²⁾ and the SRAM cell current multiplied by the number of SRAM cells,³^,⁴⁾ respectively. At a high active rate, the active switching power is dominated, while at a low active rate, the standby leakage power is dominant. An IoT device is supposed to operate in an intermittent mode so that its active rate will be low. Therefore, the power consumption of an IoT device will be dominated by standby leakage power.

**Fig. 1.** Estimated power consumption of a low-power MCU with different technologies and transistor leakage currents.
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To achieve power consumption at the µW or nW level, it is necessary to suppress leakage current by more than tenfold but maintain drive current and dynamic performance. The on-current–off-current ratio (I_on/I_off) must be high. This can be achieved by reducing the subthreshold slope (SS). The SS of MOSFET⁵⁾ is expressed by

$\begin{equation} \mathrm{SS} = \left[\frac{d(\log_{10}I_{\text{d}})}{dV_{\text{g}}}\right]^{-1} {}= \left[\frac{\partial (\log_{10}I_{\text{d}})}{\partial\psi_{\text{s}}}\cdot \frac{\partial\psi_{\text{s}}}{\partial V_{\text{g}}}\right]^{-1}. \end{equation} \tag{ 1 }$

On the rightmost side, the first term represents how much the drain current (I_d) can increase by bending the surface potential (ψ_s), which depends on the electron transport mechanism under a certain field effect, as illustrated in Fig. 2. The second term represents how much the surface potential can bend as the gate voltage (V_g) increases, which is determined by a voltage divider between the gate insulator and the substrate. There is a physical limit of SS in a conventional MOSFET. It is about 60 mV/dec at room temperature, which can be theoretically realized by assuming an ideal diffusion current from source to channel and an infinitely large gate-insulator capacitance. Because of the severe power requirement in the near future, the International Roadmap for Devices and Systems (IRDS) projects that SS will need to be 40 mV/dec by 2033,⁶⁾ as shown in Fig. 3. A transistor with a steep SS enables energy-efficient switching.⁷⁾ Therefore, the physical limit of 60 mV/dec must be overcome for the system requirement.⁸^,⁹⁾

**Fig. 2.** Schematic illustration of the physics of SS. SS can be represented by two terms: field-effect transport term and voltage divider term.
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**Fig. 3.** Roadmap of SS projected by IRDS.⁶⁾ GAA stands for gate-all-around.
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A sub-60 mV/dec SS can be theoretically achieved by engineering either the first or second term of Eq. (1). TFET¹⁰^–¹³⁾ and IMOS¹⁴^,¹⁵⁾ are examples that show a sub-60 mV/dec SS by engineering the first term, whereas the floating-body effect SOI transistor¹⁶^,¹⁷⁾ is one device that can engineer the second term. Currently, TFET is actively studied and an excellent steep SS has been achieved. However, there are several technical challenges on TFET: (1) relatively low I_on due to tunneling transport, (2) asymmetric operation between source and drain, and (3) complicated material and process requirements.

The negative-capacitance FET (NCFET) is an emerging transistor technology¹⁸^,¹⁹⁾ that can achieve a sub-60 mV/dec steep SS by engineering the second term. Together with the recent breakthrough in material development, NCFET has become one of the most promising steep-SS transistors with benefits of (1) high drive current due to conventional drift-diffusion transport, (2) symmetric operation between source and drain, and (3) low cost.

In this paper, recent studies of NCFET are widely overviewed. First, the original concept of NCFET is explained in Sect. 2. Then, recent research results are introduced in Sect. 3. Lastly, the latest findings are discussed in Sect. 4. Section 5 shows the summary.

2. Original concept of NCFET

NCFET was originally proposed by Salahuddin and Datta.¹⁸^,¹⁹⁾ The SS of a MOS transistor is simply expressed by using the gate insulator capacitance (C_ox) and substrate capacitance (C_s),

$\begin{align} \mathrm{SS} & = \left[\frac{\partial (\log_{10}I_{\text{d}})}{\partial\psi_{\text{s}}}\cdot \frac{\partial \psi_{\text{s}}}{\partial V_{\text{g}}}\right]^{-1}\\ & = 60 \cdot \left(1 + \frac{C_{\text{s}}}{C_{\text{ox}}}\right). \end{align} \tag{ 2 }$

To achieve sub-60 mV/dec, that is, SS < 60 mV/dec, the capacitances should satisfy the following conditions:

$\begin{equation} C_{\text{ox}} < 0,\quad |C_{\text{ox}}| > C_{\text{s}}. \end{equation} \tag{ 3 }$

These conditions mean that C_ox must be negative and C_s must be appropriately designed to be less than |C_ox|. If such a negative-capacitance gate insulator is available in the field-effect transistor device in Fig. 4(a), a sub-60 mV/dec steep SS can be achieved according to the simulation result shown in Fig. 4(b).¹⁹⁾ In this section, the physics of negative capacitance (NC) and the operation principle of NCFET are illustrated in the context of the original concept. The important concept of capacitance matching is discussed. The early NCFET works are introduced.

2.1. Negative capacitance

NC cannot be seen in a typical paraelectric (PE) gate insulator, but it can be seen in a ferroelectric (FE) gate insulator, as shown in Fig. 4(c).¹⁹⁾ NC in FE can be derived from phenomenological Landau free energy.²⁰⁾ Suppose you have a single-domain FE material. The space inversion symmetry is broken in FE materials. This leads to double-well free energy, which is described by the Landau free energy, as a function of the order parameter of charge Q [Fig. 4(c)-(i)], while PE has a single obvious energy minimum [Fig. 4(c)-(ii)]. Conventionally, Q in FE represents spontaneous polarization (P). If you take a derivative of the free energy of a FE capacitor connected with a power supply by an order parameter, you can obtain the force field voltage V. This Q–V curve corresponds to the P–V curve, which can be extracted from the Q–V curve measured in a FE capacitor as a hysteretic curve where remanent polarization (P_r) and coercive field (E_c) are characteristic quantities. If you take a derivative of Q by V, you can obtain the capacitance C as a coefficient to relate order parameter Q to force field V. Capacitance is positive for a PE capacitor [Fig. 4(c)-(iv)], whereas it can be negative for a FE capacitor in a certain voltage range [Fig. 4(c)-(iii)].

However, the NC effect is available only in the metastable state of the Landau free energy with a negative curvature, which is not stable with the FE capacitor itself. To utilize the NC effect in stable condition, the PE capacitor should be connected in series.¹⁸^,¹⁹⁾ If an appropriate PE capacitor is connected to the FE capacitor, the total free energy can be minimized, while NC is accessible in the FE capacitor, as illustrated in Fig. 5,²¹⁾ which shows the transition of the energy of the FE capacitor (U_FE) and the total energy of the series-connected capacitor (U_tot) as V_g increases. The FET substrate capacitance can include an interfacial oxide capacitor in series and works as a matching capacitor to the FE capacitor. Capacitance matching will be explained later.

**Fig. 5.** (Top) Calculated energies of FE capacitor (U_FE) and (bottom) total energies of series-connected FE and PE capacitor (U_tot) from zero V_g (left) to high V_g (right) bias.
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2.2. Operation principle

NCFET is almost the same as a conventional MOSFET except that the gate insulator is FE, as shown in Fig. 4(a). In this section, the operation principle of NCFET based on the original concept¹⁸^,¹⁹⁾ is explained in the form of a simple bulk FET without interfacial oxide.²²⁾ Assume that the flat-band voltage is zero. Considering charge neutrality, the polarization charge matches the substrate charge. Therefore, when you draw a P–V curve for FE and the substrate charge versus voltage curve for FET in the same graph, the cross-point represents the operation point of NCFET. These operation point and corresponding band diagrams are shown in Fig. 6. As V_g is applied, the curve for FET moves to the right and thus the operation point moves [Fig. 6(a)]. As a large V_g is applied, a more negative voltage is induced on the FE gate insulator so that the surface potential becomes larger than the applied V_g, ∂ψ_s/∂V_g > 1 [Fig. 6(b)]. This is the so-called voltage amplification. Since the transport mechanism of NCFET is just the same as that of MOSFET, i.e., drift and diffusion, the SS of NCFET can be less than 60 mV/dec at room temperature according to Eq. (1). Note that, once a sufficiently large V_g is applied and the operation point moves away from the NC region in the P–V curve, a positive voltage is applied to the FE gate insulator and ψ_s cannot exceed V_g anymore [Fig. 6(c)]. Mathematically, there will be no hysteresis, the operation is reversible, and the voltage across FE (V_fe) does not need to exceed the coercive voltage (V_c) of FE, as long as C_ox < 0 and |C_ox| > C_s are satisfied. If C_ox < 0 but |C_ox| < C_s, a steep SS can still be obtained but with hysteresis having bistable operation points.

**Fig. 6.** (Top) Operation points in P–V curves as a cross point with FET load line and (bottom) corresponding schematic band diagrams of NCFET. (a) A negative voltage is induced on the gate insulator, and then (b) the surface potential is amplified at a higher gate bias. (c) At a sufficiently high V_g, a positive voltage is induced on the gate insulator.
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2.3. Capacitance matching

Now that the FET substrate capacitance works as a matching capacitor to the FE capacitor, the substrate capacitance needs to be appropriately designed to satisfy |C_ox| > C_s. Capacitance matching²³^–²⁵⁾ can be done (1) by adjusting the FE material to the fixed substrate of FET and/or (2) by adjusting the substrate of FET to the fixed FE material. In case (1), a general guideline to realize a steep SS is that the P–V curve should be compressed, meaning that P_r should be small and E_c should be large so as to make the NC slope in the P–V curve close to that of FET. In case (2), the substrate capacitance, which typically consists of the interfacial oxide and channel capacitances, should be sufficiently large to match the capacitance of the FE gate insulator. This is important because the channel capacitance in the subthreshold region is very small owing to the low density and low capacitance of the space charge in the depletion layer. Channel design for capacitance matching will be discussed later. To design and realize capacitance matching, some matching curves are used in hand. For example, drawing the Q–V curves of the FE and FET substrate as shown in Fig. 7 ²³⁾ is useful for visualizing how closely the capacitances and charges of the FE and FET substrate match.

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2.4. Experimental evidence of negative capacitance

There are several reports that experimentally observed NC in the context of the original concept of NCFET. The NC effect was observed in a series-connected FE capacitor and a paraelectric (DE) capacitor in high-frequency C–V measurement²⁶^,²⁷⁾ as shown in Fig. 8.²⁶⁾ Generally, the series-connected capacitance becomes smaller than that of an individual capacitor. However, the FE capacitance rather enhances the DE capacitance by series connection [Fig. 8(c)], which is consistent with the simulation result [Fig. 8(b)].

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The NC effect was also observed by using the transient measurements²⁸⁾ shown in Figs. 9(a) and 9(b). The motivation to use transient measurements is that, if you sweep the external voltage applied to the FE capacitor, you can only observe the monotonic increase in P as a function of V²⁹⁾ and you will neither access the NC region in the P–V curve nor observe the NC effect. Instead of the sweeping voltage, you can sweep the charge by using a transient system. Having resistance in series, you can regulate the current and control the charge, and then measure the voltage induced on the FE capacitor. Q is calculated by integrating the measured current, and the Q–V curve of FE can be reconstructed. Although it is not possible to fully trace the S-shape NC region, the NC effect can be observed as a voltage snapback in the measured Q–V curve of FE, as shown in Fig. 9(c).²⁸⁾

**Fig. 9.** (a) Schematic of transient measurement of FE capacitor connected with series resistor. PVDF stands for polyvinylidene fluoride. P(VDF-TrFE) is a copolymer with trifluoroethylene (TrFE), which shows ferroelectricity. (b) Schematic circuit diagram corresponding to (a). (c) Current, charge, and voltage in FE capacitor can be measured and extracted from (b). The P–V curve can be reconstructed from these data by plotting the measured charge versus the measured voltage. Reprinted with permission from Ref. 28. © 2018 Springer Nature.
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2.5. Early NCFET works

Steep SS characteristics were already observed back in 2008–2010.³⁰^,³¹⁾ For example, a metal–FE-metal–insulator–semiconductor (MFMIS)-FET was fabricated by using a conventional FE material. MFMIS-FET can be seen as the device that integrates the MFM capacitor and MISFET on the same device. The MFMIS structure is useful because the internal node voltage can be monitored to observe voltage amplification. The top MFM capacitor and bottom MISFET can be independently characterized as well. By fabricating the device shown in Fig. 10(a), a sub-60 mV/dec SS was observed³⁰^,³¹⁾ in Fig. 10(b).³¹⁾ In another paper, the authors came up with the idea of connecting a discrete transistor and a FE capacitor on different chips by wire bonding, as shown in Fig. 10(c).³²⁾ Their paper also showed a sub-60 mV/dec SS with a surprisingly small hysteresis [Fig. 10(d)].

**Fig. 10.** (a) Schematic of NCFET as metal–ferroelectric–metal–insulator–semiconductor (MFMIS)-FET with internal metal gate, which serves to monitor internal node voltage. (b) Measured SS values of three different devices, which have the structure of (a) with different sizes. (a) and (b) are reprinted with permission from Ref. 31. © 2018 IEEE. (c) An MFMIS-type NCFET is implemented by wiring a discrete MOSFET sample and a FE capacitor sample. (d) Measured I_d–V_g curves of the MFMIS-FET and discrete MOSFET shown in (c). (c) and (d) are reprinted with permission from Ref. 32. © 2018 IEEE.
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3. Recent research studies of NCFET

Until recently, NCFET did not attract much attention because it uses the FE gate insulator and it was difficult to find a FE material compatible with the CMOS process. However, there was a material breakthrough; ferroelectricity was discovered in a HfO₂ film, which is a mature technology as a high-k gate dielectric in the CMOS process. Because of this breakthrough, NCFET has now become one of the most promising steep-slope transistors. In this section, FE-HfO₂ is briefly introduced. The design of NCFET with FE-HfO₂ is explained. Recent reports of sub-60 mV/dec SS are introduced. Then, several design options and considerations for NCFET are discussed.

3.1. Material breakthrough: FE-HfO₂

It is known that crystallized HfO₂ shows a higher dielectric constant than amorphous HfO₂. There were studies on utilizing crystallized HfO₂ as a next-generation high-k gate dielectric for CMOS process integration.³³⁾ In the course of developing such a high-k gate dielectric for either logic or DRAM application, ferroelectricity has been discovered in a HfO₂ thin film.³⁴^,³⁵⁾ Figure 11(a) shows an example of sub-10 nm FE-HfO₂. By doping with Si, Al, or Zr, and with an appropriate metal electrode and annealing conditions, crystallized HfO₂ shows ferroelectricity. HfZrO₂ is a popular FE-HfO₂ material that shows ferroelectricity and anti-ferroelectricity depending on the Zr concentration. Typically, an orthorhombic phase appears in a FE-HfO₂ thin film. Unlike a conventional perovskite material, the displacement of an oxygen anion instead of a metal cation is considered to be the origin of ferroelectricity.³⁶^,³⁷⁾

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There are several advantages in FE-HfO₂. Ferroelectricity can be seen in a sub-10-nm-thick HfO₂ thin film³⁵⁾ without causing much leakage current due to a wide band gap. FE-HfO₂ has a large E_c, and thus the memory window is large even with a very thin film. This means that FE-HfO₂ is highly scalable and suitable for high-density logic and memory applications. FE-HfO₂ is thermally stable between 600 and 1000 °C depending on the dopant.³⁸^,³⁹⁾ FE-HfO₂ is compatible with the back-end H₂ annealing process.⁴⁰⁾ Moreover, FE-HfO₂ can be realized using standard CMOS-compatible metal electrodes such as TiN and TaN, which facilitate the patterning of a metal gate and a back-end interconnect.⁴¹⁾ Therefore, FE-HfO₂ is regarded as the most suitable gate insulator for NCFET.

Similarly to the method explained in Sect. 2.4, the NC effect has been observed by transient characterization,⁴²^,⁴³⁾ as shown in Fig. 12.⁴²⁾ Instead of by sweeping voltage across FE-HfO₂, by regulating the current through the capacitor and obtaining the voltage across the capacitor, NC was observed in FE-HfO₂ as a voltage snapback in the measured Q–V curve of FE-HfO₂. Here, note that the observed NC effect in Figs. 9 and 12 can be explained by an alternative model instead of the original NC model based on Landau free energy, which will be discussed later.

3.2. NCFET with FE-HfO₂

Thanks to the discovery of FE-HfO₂, NCFET has become one of the most promising steep-SS transistors because of (1) high I_on/I_off with high I_on, (2) CMOS-compatible material and process, and (3) minimum circuit design modification owing to the symmetric device structure and operation. The NCFET design was explored and a growing number of papers have demonstrated a sub-60 mV/dec steep SS.

3.2.1. Device design.

NCFET is designed on the basis of the material parameters of FE-HfO₂, which are available for various material and process conditions. The FE-HfO₂ thickness and channel structure are also options for design. These parameters should be optimized to satisfy capacitance matching. For future ultralow-power technologies, the target supply voltage (V_dd) will be less than 0.6 V.⁶⁾ The model of NCFET can be built as a combination of a FE capacitor and a FET channel.¹⁹^,²³^,⁴⁴^–⁴⁶⁾ Some open sources are also available.⁴⁷⁾ The FE capacitor can be analytically modeled by the Landau–Khalatnikov equation⁴⁸⁾ and the FET channel can be modeled by an analytical equation, SPICE model, or TCAD. The Landau–Khalatnikov equation is expressed as

$\begin{align} \rho \frac{dP}{dt} & = -\frac{dG}{dP}, \end{align} \tag{ 4 }$

$\begin{align} G(P,E) & = \frac{\alpha}{2}P^{2} + \frac{\beta}{4}P^{4} + \frac{\gamma}{6}P^{6} - E\cdot P. \end{align} \tag{ 5 }$

Here, ρ is the switching resistivity that determines the dynamic response of the polarization in the FE material, G is the Landau free energy, and α, β, and γ are the Landau parameters that determine the static property of the FE material.

As a design sample, Fig. 13(a) shows the contour plot of I_on/I_off for a HfO₂-based NCFET as a function of the material parameters P_r and E_c. A design space exists where NCFET shows a higher I_on/I_off than a conventional MOSFET even at V_dd = 0.2 V.⁴⁹⁾ A smaller P_r is preferred for charge matching between the FE and the FET channel, while E_c should be adjusted to avoid hysteresis. With a standard FET channel design, the material parameters can be chosen from the existing reported values of FE-HfO₂ for I_on/I_off, as shown in Fig. 13(b).²²⁾

3.2.2. Experimental demonstration of sub-60 mV/dec steep SS.

Since 2015, there have been a number of papers that demonstrated a sub-60 mV/dec steep SS in NCFETs with FE-HfO₂.⁵⁰^–⁶¹⁾ Here are some examples. In 2015, with 5 nm FE HfZrO₂, a sub-60 mV/dec steep SS was observed in NCFET with a bulk Si FET channel as well as a Ge channel.⁵⁰⁾ Hysteresis in I_d–V_g characteristics is as small as ∼0.1 V. NCFET was also fabricated with HfZrO₂ and a bulk FinFET channel.⁵¹⁾ Performance enhancement was clearly observed in both NFET and PFET. In 2016, FE HfZrO₂ was scaled down to sub-2 nm, and a sub-60 mV/dec steep SS was clearly observed without hysteresis at all.⁵²⁾ A hysteresis-free NCFET was also demonstrated with a Ge channel.⁵³⁾ In 2017, FE HfAlO₂ was employed for NCFET. The potential benefit of HfAlO₂ is that it can endure a higher thermal budget, which may be required for reliability improvement. Again, a hysteresis-free sub-60 mV/dec steep SS was observed in NCFET with HfAlO₂.⁵⁴^,⁵⁵⁾

Figures 14(a) and 14(b) show representative data obtained from the measured I_d–V_g curves of an n-type NCFET³⁰^,³¹^,⁵⁴^–⁶¹⁾ for forward and backward V_g sweeps, respectively, as well as a reference 14 nm CMOS.⁶²⁾ Figures 15(a) and 15(b) show the SS extracted from the measured I_d–V_g curves in Figs. 14(a) and 14(b), respectively. Most of the devices show a sub-60 mV/dec steep SS in the range of more than 2 orders of magnitude of deep subthreshold current.

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3.3. Options for device integration

3.3.1. Gate stack structure: MFIS versus MFMIS.

When exploring NCFET, there are two major architectures: MFIS and MFMIS. MFIS stands for metal-FE-insulator-semiconductor and MFMIS stands for metal–FE-metal–insulator–semiconductor. The only difference is whether the structure has an internal metal or not, as shown in Fig. 16(a),⁶³⁾ where MFIS and MFMIS are shown in (i) and (ii), respectively. As introduced in Sect. 2.5, early NCFET studies often used MFMIS. For MFMIS-FET, the MFM capacitor and MISFET can be independently designed and fabricated. Moreover, the internal node voltage can be directly measured, which is valuable information to confirm voltage amplification. However, if NCFET is considered to be introduced to advanced CMOS technologies that employ the replacement gate process with the sub-20 nm gate length,⁶²⁾ there will be no space to fill the gate trench with an internal metal. Moreover, the internal metal allows charge injection and accumulation, which prevent the expected NCFET operation. Therefore, MFIS-FET is the viable choice, although it is not possible to independently design and characterize the FE and FET channel.

**Fig. 16.** (a) Simulated contour plot of electrostatic potential of NCFET (i) without and (ii) with internal metal. The arrows show electric field vectors. (a) is reprinted with permission from Ref. 63. © 2018 IEEE. (b) Simulated I_d–V_g curve of NCFET with and without internal metal. (c) Simulated (i) SS of NCFET versus I_d and (ii) I_on/I_off of NCFET without internal metal for different K_p values, with internal metal, and standard MOSFET. K_p represents the strength of the interaction of FE domains. (d) Simulated (i) DIBL and (ii) output resistance of NCFET without internal metal for different K_p values, with internal metal, and standard MOSFET. (b)–(d) are reprinted with permission from Ref. 65. © 2018 IEEE.
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From the device operation viewpoint, there is a distinct difference between MFIS and MFMIS in terms of the distribution of polarization in domains along the channel direction under drain-to-source bias (V_ds).⁶³^–⁶⁵⁾ MFMIS has an internal metal where the potential is uniform. Since the potential difference between the top electrode and the internal metal is uniform along the channel, the polarization of the FE layer is uniform along the channel. Thus, surface potential can be amplified in nearly the entire channel region. On the other hand, MFIS does not have the internal metal so that the polarization of FE is not uniform along the channel. Thus, surface potential can be amplified mostly near the source region. The simulation work was performed by modeling the multidomain as a one-dimensional domain array with domain interaction.⁶⁵⁾ The work revealed that, if there is no gate leakage or charge injection to the internal metal, MFMIS is superior to MFIS in terms of subthreshold characteristics. The sub-60 mV/dec steep SS and high I_on/I_off can still be achieved with MFIS as long as the domain interaction is sufficiently strong, as shown in Figs. 16(b) and 16(c).⁶⁵⁾ A negative DIBL and a negative differential resistance can be also observed in MFMIS and MFIS with a strong domain interaction, as shown in Fig. 16(d), which will be revisited later. There are several experimental studies on the difference between MFIS and MFMIS, which support the simulation result.⁵⁷^,⁵⁸⁾

3.3.2. Channel engineering: 2D versus 3D.

In Sect. 2.3, the importance of capacitance matching is explained. With fixed material parameters for the FE layer, the substrate capacitance should be designed so as to satisfy the capacitance matching condition. In general, the substrate charge and capacitance in the deep subthreshold region are relatively much smaller than those of FE for bulk FET. Although FinFET is the current standard transistor, the channel region is fully depleted, and the charge and capacitance of the substrate are small. Therefore, it is relatively difficult to achieve charge and capacitance matching with the fin channel and FE gate insulator. On the other hand, a planar SOI transistor has a better chance of capacitance matching. If the SOI and BOX layers are thinned down with the bottom substrate highly doped, the substrate capacitance becomes relatively large even in the subthreshold region. The simulation study demonstrated that a thin body and a thin BOX SOI NCFET [Fig. 17(a)-(i)] can achieve a steeper SS than a fin NCFET [Fig. 17(b)-(ii)] with the fixed FE parameters and smaller BOX thickness, as shown in Figs. 17(b) and 17(c).⁶⁶⁾ This is mainly because the SOI NCFET has a larger substrate capacitance with a thin BOX and better capacitance matching. Thus, the NC effect is beneficial to mature planar SOI transistor technologies, and an ultralow-power NCFET can be realized by a low-cost process. There is an extra benefit for the thin SOI and BOX transistors, which is substrate biasing.⁶⁷^,⁶⁸⁾ Since such thin SOI and BOX structures allow strong substrate coupling, body capacitance can be tuned by substrate bias, which opens a wider design space.⁶⁹⁾ In NCFET, the substrate bias effect on threshold voltage (V_th) can be opposite to that in conventional MOSFET depending on the FE layer thickness and capacitance matching, as shown in Figs. 17(d) and 17(e),⁶⁹⁾ which provides an additional option for device design. Moreover, NCFET has also been experimentally demonstrated with 2D materials such as MoS₂ with a clear sub-60 mV/dec steep SS.⁵⁷^,⁶⁰^,⁷⁰⁾ This indicates that the NC effect is not dependent on the substrate material or structure; rather, the NC effect can be used as a performance booster.

**Fig. 17.** (a) Schematic of device structures of (i) planar SOI NCFET and (ii) SOI NC FinFET. SOI and BOX stand for silicon-on-insulator and buried oxide, respectively. (b) Simulated I_d–V_g characteristics of SOI NCFET and reference MOSFET with different BOX thicknesses. (c) SS versus BOX thickness for SOI NCFET and NC FinFET. (a)–(c) are reprinted with permission from Ref. 66. © 2018 The Japan Society of Applied Physics. (d) Schematic of thin body SOI FET with 2D channel material. (e) Simulated V_th of SOI NCFET with thin body and thin BOX versus V_bs as a function of FE layer thickness. (d, e) are reprinted with permission from Ref. 69. © 2018 IEEE.
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3.3.3. Negative capacitance as a performance booster.

As mentioned in the last subsection, the NC effect can be an additive performance booster on any kind of charge-based field-effect transistor device. Moreover, it is possible to combine the NC effect with other steep-SS transistors such as TFET. Thus far, each type of steep-SS transistor has been independently studied by engineering each term in Eq. (1). If both terms in Eq. (1) can be engineered by synthesizing different types of steep-SS transistors, a supersteep-SS transistor can be realized. Therefore, combining TFET and the NC effect in the same device has been proposed.⁷¹^,⁷²⁾ Although TFET utilizes tunneling transport, it still relies on the field effect for band bending. The NC TFET was designed on the basis of the vertical TFET with a FE gate insulator. The vertical TFET has a highly doped p–n junction on the source side under the gate, which facilitates the charge and capacitance matching in the deep subthreshold region. In fact, the simulation demonstrates that the NC TFET can better improve SS than TFET by more than 4 orders of the current level, as shown in Fig. 18(a).⁷²⁾ Energy efficiency, which is energy per switching, is greatly improved in Fig. 18(b). Recently, the NC TFET has been experimentally demonstrated in the device shown in Fig. 18(c), where on-current and SS are significantly improved as shown in Figs. 18(d) and 18(e), respectively.⁷³⁾ The NC effect proves to be an additive performance booster, which is a very important property as persistent technology for many generations.

**Fig. 18.** (a) Comparison of simulated I_d–V_g characteristics of NCTFET with those of conventional TFET. TFET stands for tunnel FET. (b) Simulated energy per switching, which is energy efficiency, for NCTFET compared with those for conventional TFET and SOTB transistor. (c) Schematic of NCTFET, which consists of discrete FE capacitor and Si TFET. (d) Measured I_d–V_g characteristics and (e) SS of NCTFET illustrated in (c) and reference TFET. (a, b) and (c)–(e) are reprinted with permission from Refs. 72 and 73, respectively. © 2018 IEEE.
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3.4. Device considerations

NCFET is expected to be a promising steep-SS transistor with an appropriate design as explained in Sect. 3.2.1, and a steep SS has indeed been experimentally observed, as mentioned in Sect. 3.2.2. However, there are several device considerations to bring NCFET to manufacturable CMOS technologies and practical applications. In this section, operation speed, device scalability, short-channel effect, reliability, and variability are discussed.

3.4.1. Operation speed.

From the original concept of NCFET, the latter should be able to drive a higher static I_on at a lower V_dd. In other words, energy-efficient switching is possible in the NCFET CMOS circuit. In fact, circuit simulation with the NCFET transistor model showed faster ring oscillator operation at lower power and V_dd.⁷⁴⁾ However, it is known that ferroelectricity originates from ionic displacement and domain dynamics.⁷⁵^–⁸⁰⁾ Because of the dynamics of charged ions and domains, the frequency range in which the polarization in FE can respond to is limited to microwave frequency. Compared with the standard MOSFET that uses the PE gate insulator with electronic displacement, the operation speed of NCFET may be limited to a lower frequency by the dynamics of polarization in the FE gate insulator instead of CV/I estimated from the static I_on. Therefore, it is important to model the dynamic characteristics of NCFET and predict the performance limit.⁴²^,⁸¹^–⁸⁴⁾ The dynamic characteristics of NCFET are modeled by the Landau–Khalatnikov equation [Eqs. (4) and (5)]. ρ is the dynamic parameter representing switching resistance. ρ can be extracted from the transient measurement of the FE capacitor connected to known resistance in series, as shown in Fig. 19(a), and fitting the transient model to experimental results, as shown in Fig. 19(b).⁴²⁾ A multidomain is also implemented in the model by considering domain interaction energy.⁸¹⁾ The static NCFET model can be extended to a dynamic one by including the dynamic term of dP/dt. The I_d–V_g characteristics of NCFET were obtained by modeling and simulation with the extracted ρ value as shown in Fig. 19(c). The operation frequency of NCFET without causing a very large hysteresis can be on the order of >1–10 MHz range, as shown in Fig. 19(d),⁴²⁾ which may be suitable for low-speed but ultralow-power applications such as IoT edge devices. There are some experimental studies on the operation speed of NCFET,⁵²^,⁵⁸⁾ which indicates that NCFET shows a larger hysteresis at a higher V_g sweep rate even though quasi-static measurement shows nonhysteresis I_d–V_g curves, which verifies the dynamic NCFET model mentioned above. For high-speed applications such as that in the GHz range, ρ needs to be orders of magnitude smaller. Thus far, the sample size in the transient measurement is quite large (on the order of microns). To accurately characterize a higher frequency response of polarization and extract intrinsic dynamic parameters to estimate operation speed, the measurement of the nanoscale FE capacitor without being limited by RC delay will be needed. Sub-µs polarization switching has been observed by careful measurement⁸⁰⁾ for a PZT material. Sub-µs polarization switching has also been observed in HfO₂-based FeFET memory, as shown in Fig. 20(a). A 10–100 ns program and erase operation has been demonstrated, as shown in Figs. 20(b) and 20(c).⁸⁵⁾

**Fig. 19.** (a) Schematic of transient measurement circuit of FE-HfO₂ capacitor, where resistor is connected to FE capacitor. Current through the FE capacitor is monitored. The charge of the FE capacitor is calculated by integrating current. Voltage is calculated by subtracting the voltage drop of the resistor from the applied voltage. (b) Measured current waveform and current waveform simulated using a multidomain model with nearest-neighbor domain interaction. (c) (Left) Simulated Ψ_s and (right) I_d versus V_g for different V_g sweep frequencies using ρ extracted by fitting in (b). (d) Extracted voltage hysteresis in I_d–V_g curves in (c) with varying dynamic parameter ρ. Reprinted with permission from Ref. 42. © 2018 IEEE.
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**Fig. 20.** (a) Cross-sectional TEM image of a 28 nm FeFET. (b) Measured I_d–V_g curves of FeFET after erase and program pulses. (c) Measured memory window map of FeFET as a function of pulse width and erase/program voltage level. Reprinted with permission from Ref. 85. © 2018 IEEE.
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3.4.2. Device scalability.

If the NC effect is to be employed in advanced CMOS technology, the process integration scheme must be taken into account. The current CMOS technology uses the FinFET architecture with the gate-last replacement-gate (RMG) process.⁶²^,⁸⁶⁾ In the RMG scheme, a dummy polygate is pulled out after source and drain formation, and interlayer dielectric deposition and planarization. Then, the gate trench is filled with a high-k gate dielectric, a metal gate to control the work function, and a low-resistivity interconnect metal. The gate trench width becomes less than 20 nm, which is very small. It is unknown if the NC gate stack can be filled in such a narrow gate trench and if there is any design space. Then, the NC FinFET was modeled and simulated in the structure shown in Fig. 21(a). The design sample is shown in the contour plot of I_on/I_off in Fig. 21(b). Owing to the property of FE-HfO₂, there exists a design space with practical material parameters and thickness for a higher I_on/I_off in the NC FinFET than in the conventional FinFET, even at V_dd = 0.2 V.⁸⁷⁾ Theoretically, the NC FinFET can be scaled down to a gate length (L_g) less than 10 nm. The NC nanowire FET was also modeled and simulated in the structure shown in Fig. 21(c), and a similar conclusion was obtained with a tight pitch nanowire, as shown in Fig. 21(d).⁸⁸⁾

**Fig. 21.** (a) Schematic of a double-gate NC FinFET with replacement gate scheme for simulation. (b) Simulated contour plot of I_on/I_off of NC FinFET as a function of interfacial layer (T_ox) thickness and FE layer thickness (T_fe). The design constraint by L_g is drawn by dotted lines. (a, b) are reprinted with permission from Ref. 87. © 2018 The Japan Society of Applied Physics. (c) Schematic of a gate-all-around nanowire NCFET for simulation with tight nanowire pitch. R is the radius of the nanowire. (d) Simulated contour plot of I_on/I_off of nanowire NCFET as a function of nanowire diameter (2R) and T_fe. The design constraint by the nanowire pitch is drawn by dotted lines. (c, d) are reprinted with permission from Ref. 88. © Elsevier.
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3.4.3. Short-channel effect.

When it comes to device scalability, the short-channel effect (SCE) must be addressed. In advanced CMOS technology, SCE becomes severe as L_g is scaled down. The pace of L_g scaling becomes slow at around 20 nm.⁸⁹⁾ It is important to understand how the NC effect has an impact on SCE in a scaled transistor. Theoretical studies revealed very interesting characteristics in the short-channel NCFET.⁶³^,⁹⁰⁾ In the short-channel NCFET, capacitance matching becomes intricate because parasitic capacitances and drain coupling are involved. However, this situation turns out favorable for capacitance matching and obtaining a steep SS. In fact, a short L_g NCFET shows a steeper SS than a short L_g conventional MOSFET, as shown in Figs. 22(a) and 22(b)-(i).⁶³^,⁹⁰⁾ Moreover, the SS of NCFET can be improved as L_g is scaled down. This is because a relatively larger parasitic capacitance than the substrate capacitance facilitates capacitance matching in the subthreshold region. In addition, the L_g dependence on the V_th and DIBL of NCFET is different from that of the conventional MOSFET, as shown in Fig. 22(b)-(ii). At a small L_g, while the conventional MOSFET shows V_th roll-off and a positive DIBL, the NCFET shows V_th roll-up and a negative DIBL.⁶³^,⁹⁰⁾ The reason for the V_th roll-up is that, for the same Ψ_s under the threshold condition, less charge is induced in the FE layer, and thus the voltage across the FE gate insulator (V_FE) increases in the positive direction as L_g decreases and the drain coupling capacitance relatively increases. The reason for the negative DIBL can be explained in a similar way because, as V_ds increases, the drain coupling relatively increases at a given L_g. A negative DIBL turns out to be a negative differential resistance (NDR) in I_d–V_d output characteristics, as shown in Fig. 22(c)⁶³⁾ because, as V_ds increases, V_th does not decrease but rather increases in NCFET. These results imply that SCE can be compensated by the NC effect, which will be crucial for extending CMOS scaling and beneficial for analog circuit application. If SCE is overcompensated, however, negative DIBL and NDR largely come into play, and circuit design needs to be reconsidered.

**Fig. 22.** (a) Simulated I_d–V_g curves of (i) conventional FinFET and (ii) NC FinFET with different L_g values. (b) Simulated (i) SS and (ii) DIBL versus L_g for conventional FinFET and NC FinFET. (c) Simulated I_d–V_d curves of (i) conventional FinFET and (ii) NC FinFET with L_g = 10 nm. Reprinted with permission from Ref. 63. © 2018 IEEE.
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3.4.4. Reliability.

FE has an inherent challenge in itself with regard to reliability. Because of the mechanical movement of ions in the thin layer, characteristic degradations such as imprint and fatigue are concerns.⁹¹⁾ Particularly for logic application, the endurance criterion is more severe than for memory application. The reliability of FE-HfO₂ has been widely reported. Thus far, 10⁴–10⁵ times endurance has been reported for memory applications of FeFET, as shown in Fig. 23(b),⁹²⁾ which is obviously insufficient for logic application, while the retention time is sufficiently long, as shown in Fig. 23(a). HfO₂ is known to have an inherent defect of oxygen vacancy. Since the physical mechanism of ferroelectricity in HfO₂ originates from oxygen anions, controlling defects such as oxygen vacancy in HfO₂⁹³^,⁹⁴⁾ and improving the reliability are the most critical tasks to bring NCFET into the development and manufacturing phase.

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3.4.5. Variability.

A steep-SS transistor is known to be vulnerable to process variability because of its steep SS characteristics.⁹⁵⁾ Even with a very small V_th variation, the subthreshold and leakage currents will vary much more than in the conventional MOSFET at low-V_dd operation. In fact, the FE gate insulator should be polycrystalline, while the standard high-k gate insulator is used as an amorphous dielectric, which causes an additional source of variability due to fluctuations of the crystalline phase and orientation. The variability issue of FE-HfO₂ has been discussed for memory application.⁹⁶^,⁹⁷⁾ However, NCFET may have the capability to suppress process variability owing to its unique mechanism. For instance, FinFET has process variability originating from fin LER, gate LER, and gate polygrain variation. Short-channel characteristics such as V_th, DIBL, and SS are sensitive to fin LER. However, it has been reported that variability in FinFET can be suppressed by employing the NC gate stack on FinFET.⁹⁸⁾ Figures 24(a)-(i) and 24(a)-(ii) show raw I_d–V_g data of conventional FinFET and NC FinFET, respectively. Figure 24(b) shows the statistical analysis of linear V_th, SS, DIBL, and saturation V_th. The standard deviation was smaller in NC FinFET than in conventional FinFET for all indicators of V_th, SS, and DIBL. This is attributed to the negative feedback mechanism by the NC effect. In NCFET, Ψ_s is amplified at the applied V_g by the NC effect. If there is Ψ_s variation by process variability, on the other hand, the voltage fluctuation with regard to V_g becomes small. Such variability compensation in NCFET will be crucial to securing a margin for low-V_dd operation.

**Fig. 24.** (a) Simulated I_d–V_g curves of 150 samples of (i) FinFET and (ii) NC-FinFET. (b) Statistical distributions of (i) V_th (lin), (ii) SS, (iii) DIBL, and (iv) V_th (sat) extracted from (a). The red and blue colors indicate NC-FinFET and normal FinFET, respectively. The mean value and standard deviation are indicated in each figure. Reprinted with permission from Ref. 90. © 2018 IEEE.
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3.5. State-of-the-art NCFET: 14 nm NC FinFET

Theoretically, NCFET should work in the short-channel regime, and the experimental demonstration of short-channel NCFET was greatly desired to judge if the NCFET technology can be brought from the early stage of research to the next stage of development. Recently, NCFET has been experimentally demonstrated based on 14 nm bulk FinFET technology as shown in Fig. 25(a).⁶¹⁾ NC FinFET shows a steeper SS than the reference FinFET, as shown in Figs. 25(b) and 25(c). The ring oscillator (RO) with NCFET demonstrated competitive performance, as shown in Fig. 25(d).⁶¹⁾ It was also reported that there was no significant reliability degradation. There is, however, a possibility that the performance enhancement comes from a higher-k effect instead of an NC effect. Although further characterization and optimization will be needed to verify the NC effect, this is a great step toward manufacturable NCFET technology.

**Fig. 25.** (a) Cross-sectional TEM image of an NC FinFET based on 14 nm bulk FinFET technology. The cross section was cut along the fin and perpendicularly to the gate. The 7–8-nm-thick bright layers are FE in dark field. The inset shows the magnified view around the FE layer (black region) in bright field. (b) Measured I_d–V_g curves of NCFET and reference MOSFET. (c) Measured SS versus I_d for NC FinFET (red) and conventional FinFET (black). Many sample data are overlapped in this figure for each. (d) Measured ring oscillator (RO) frequency versus gate overdrive voltage. Reprinted with permission from Ref. 61. © 2018 IEEE.
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4. Latest findings of NCFET

In the previous sections, recent NCFET works were reviewed. A steep SS has been experimentally observed in long-channel devices in many reports. A 14 nm NC FinFET has also been demonstrated. However, such experimental results may not be completely understood on the basis of the original concept of the static NC effect based on the Landau free energy model. For example, capacitance matching is expected to be achieved at around V_th and in the inversion region with a standard channel design in a long-channel transistor unless the transistor has a large parasitic capacitance. However, the experimental results of a long-channel NCFET show a steep SS in the deep subthreshold region as shown in Figs. 14 and 15. In addition, from the microscopic viewpoint, the NC effect based on the Landau free energy model with a single domain may not be applicable because such a long-channel device should have multidomain structures. Therefore, the physical model of the NC effect is still being investigated to provide reasonable and comprehensive explanations for the previously reported experiments. In this section, the latest findings of NCFET are reviewed.

4.1. Multidomain effect

As briefly mentioned in Sect. 3.3.1, the multidomain effect cannot be ignored in real devices, while the original concept of the NC effect based on the Landau free energy model in Sect. 2.1 is derived from the single-domain structure. Within the framework of the Landau free energy model, the NC effect is not available in the multidomain if each domain has no interaction.⁹⁹⁾ If the domain interaction is sufficiently strong and the multidomain acts almost like a single domain, a steep SS, a high I_on/I_off [Fig. 16(c)], and other unique phenomena such as negative DIBL and NDC can be observed, as shown in Fig. 16(d).⁶⁵⁾ However, it is physically natural that FE has domain switching and antiparallel configuration in the multidomain in the course of polarization switching from the thermodynamic viewpoint. To be consistent with the material physics of FE, the multidomain should be considered in the NCFET model. However, note that if a device is indeed fabricated with a single-domain ferroelectric in a small device size, the Landau free energy model may still hold, for which there has been no clear evidence yet.

4.2. Charge injection and major loop

From the original concept of the NC effect, with an appropriate capacitance matching, NCFET has, in principle, no hysteresis and does not need to pass V_c, which possibly allows ultralow-voltage operation. This model is, however, contradictory to the conventional theory of FE, in which a sufficiently large voltage should be applied to the FE layer for polarization switching. The V_g sweep amplitude dependence on I_d–V_g characteristics has been experimentally studied in NCFET with FE-HfO₂.¹⁰⁰⁾ In Figs. 26(a) and 26(b), with a small amplitude of V_g sweep, NCFET does not show a steep SS but rather shows a clockwise hysteresis with charge injection. On the other hand, with a sufficiently large amplitude of V_g sweep, NCFET shows a steep SS with a ferroelectric counterclockwise hysteresis. These results suggest that FE needs the initialization of polarization and a large voltage sweep to track its major loop before polarization switching for a steep SS. The very small or zero hysteresis reported in steep-SS NCFET was regarded as the outcome of a very small FE layer thickness and/or a small E_c under a capacitance matching condition, but it may be the outcome of the compensation of ferroelectric hysteresis by the V_th shift due to charge injection.

**Fig. 26.** (a) Measured I_d–V_g characteristics of MFIS NCFET with different V_g sweep ranges. (b) Measured SS of MFIS NCFET with different V_g sweep ranges. (c) Measured I_d–V_g characteristics of MFIS NCFET with different V_g sweep time steps. (d) Measured SS versus V_g sweep time step of MFIS NCFET. (a, b) and (c, d) are reprinted with permission from Refs. 100 and 101, respectively. © 2018 IEEE.
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4.3. Transient effect

Since the direct measurement of the NC effect was reported²⁸^,⁴²^,⁴³⁾ as explained in Sects. 2.4 and 3.1, it has been argued that the NC effect is caused by the transient characteristics of the FE capacitor instead of tracking the S-shape in the P–V curve. Thus, the physical model of the transient NC effect has been reconsidered by using a classical macroscopic and transient model for FE as an alternative to the original concept of the static NC effect based on the Landau free energy model.

4.3.1. Transient effect in experiments.

The transient effect has been experimentally studied in NCFET. Figure 26(c)¹⁰¹⁾ shows the measured I_d–V_g curves with different V_g sweep times. Figure 26(d) shows SS as a function of sweep time.¹⁰¹⁾ There exists a sweep time window where a steep SS can be observed. It is claimed that two mechanisms compete and limit the time window: domain switching and screening charge compensation. If the sweep time is very fast, polarization switching cannot follow the V_g sweep and thus no steep SS is observed within the V_g sweep time. If the sweep time is very slow, free charge can completely screen the polarization charge and thus no steep SS is observed within the V_g sweep time. The study indicates that, if the polarization switching delay time is comparable to the V_g sweep time, then a steep SS is observed owing to the incomplete screening of the polarization charge, which can be understood on the basis of the conventional theory of FE as described below.

4.3.2. Time-dependent nonlinear capacitor and resistor model.

As mentioned in Sect. 4.1, the NC effect in the original concept assumes that all domains respond to the electric field and switch simultaneously similarly to a single domain. However, to realize such switching, FE must pay a high energy cost to pass the local maximum. It is physically natural that FE has domain switching and antiparallel configuration in the multidomain in the course of polarization switching from the thermodynamic viewpoint,¹⁰²^–¹⁰⁴⁾ as shown in Fig. 27(a).¹⁰³⁾ It was claimed that the NC effect was experimentally observed as a consequence of polarization switching by the nucleation and growth of reverse domains, and the incomplete screening of polarization charge.¹⁰⁵⁾ The simple model for the FE capacitor was built by a series-connected time-dependent variable resistor and capacitor that reflect the actual time-dependent and nonlinear FE properties, as shown in Fig. 27(b).¹⁰³⁾ By transient simulation, this positive capacitance model well reproduced the NC effect in the voltage and current of the FE capacitor as shown in Figs. 27(c) and 27(d).¹⁰³⁾ The current shows a delayed peak of polarization switching and the voltage correspondingly drops, which is regarded as the NC effect.

**Fig. 27.** (a) Schematic illustration of two possible paths of FE polarization reversal: via metastable state by flipping polarization of all domains simultaneously (red) or via antiparallel configuration by flipping polarization of domains gradually (blue). (b) Equivalent circuit of transient measurement circuit with time-dependent capacitor and resistor model for FE capacitor. (c) Measured and simulated waveforms of voltage across FE capacitor and (d) current through FE capacitor. Reprinted with permission from Ref. 103 under the Creative Commons License.
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4.3.3. Polarization switching delay model.

The hypothesis that the transient NC effect is the cause of the steep SS is considered and verified using several models and simulations. The Preisach model is one of the classical models of FE for memory application¹⁰⁶⁾ and has recently been revisited to examine the transient NC effect. This model is a macroscopic one for FE, which takes the form of a series-connected variable resistor and capacitor as shown in Fig. 29(a), similarly to that in Sect. 4.3.2. The model formally includes the multidomain effect and polarization switching delay due to domain nucleation and propagation:

$\begin{align} P(V_{\text{aux}}) & = P_{\text{s}}\tanh [w(V_{\text{aux}}\pm V_{\text{c}})], \end{align} \tag{ 6 }$

$\begin{align} w & = \frac{1}{2V_{\text{c}}}\ln \frac{P_{\text{s}} + P_{\text{r}}}{P_{\text{s}} - P_{\text{r}}}, \end{align} \tag{ 7 }$

$\begin{align} \frac{dV_{\text{aux}}}{dt} & = \frac{1}{\tau}(V_{\text{fe}} - V_{\text{aux}}). \end{align} \tag{ 8 }$

Here, P is the polarization charge density and ± denotes the forward or backward voltage sweep. Equation (6) represents a quasi-static P–V curve of the FE capacitor. w represents the slope of the tanh function, which takes multidomain switching into account. P_s and P_r are the saturation and remanent polarization charge densities, respectively. V_aux is the auxiliary voltage across the variable capacitor to model the polarization switching delay. V_fe is the total voltage across the FE capacitor. τ represents the time constant of polarization switching delay.

The transient measurement circuit of the series-connected resistor and FE capacitor stack of a MFIS capacitor in Fig. 28(a) was simulated using the Preisach model of FE.¹⁰⁷⁾ Figure 28(b) shows the simulated waveforms in response to a rectangular voltage pulse. A temporary drop occurs in the voltage across the FE capacitor stack (V_F). This is regarded as a transient NC effect and can be described as follows: first, displacement current flows through and charges the FE capacitor stack, and V_F increases. When polarization switching occurs with delay, a large current flows through the resistor, which temporarily causes a large voltage drop on the resistor. Thus, V_F decreases. After polarization switching occurs, the FE capacitor stack is gradually charged again and V_F increases. Figure 28(c) shows the reconstructed P–V curve in the same way as in Sects. 2.4 and 3.1. Therefore, it is possible to explain the voltage snapback in Figs. 9 and 12 as a transient NC effect. Moreover, even without a resistor in Fig. 28(a), a transient NC effect was observed in a series-connected FE–DE capacitor of the MFIS structure by simulation, as shown in Fig. 28(e).¹⁰⁰⁾ The surface potential in the MFIS structure was amplified by the transient NC effect and voltage gain in response to a triangular voltage pulse, as shown in Figs. 28(d) and 28(f).¹⁰⁰^,¹⁰⁷⁾ Such a transient NC effect was observed in simulation in several reports.¹⁰⁷^–¹⁰⁹⁾

The transient NC effect in the series-connected FE–DE capacitor can be described in detail as follows [Figs. 29(a) and 29(b)]:¹¹⁰⁾ Fig. 29(a) shows the model of the ferroelectric capacitor. Suppose polarization is initialized by applying a sufficiently large negative voltage and a triangular wave pulse is input. When sweeping voltage in the positive direction, V_fe is increased by charging PE capacitors by the displacement current. When the polarization switching current (dP/dt) flows with delay, dP/dt temporarily exceeds the free carrier current (dQ/dt) and V_fe decreases due to the depolarizing field because the polarization charge is not fully compensated instantaneously by the free carrier charge, but the charge balance of Q = εE + P needs to be satisfied. In the backward sweep direction, a similar explanation can be made. This can be seen as voltage gain, and thus a transient NC effect on the transistor. A steep SS is indeed observed in the simulation of MFIS-FET with polarization switching delay (τ) if τ is on the same order as the V_g sweep speed, as shown in Fig. 29(c).¹¹⁰⁾ If polarization switching is very fast (τ = 0) compared with the V_g sweep, on the other hand, no steep SS is observed, but only a memory window hysteresis is observed as shown in Figs. 29(c) and 29(d).¹¹⁰⁾ Similarly, suppose τ is fixed and the V_g sweep speed varies. A steep SS is observed with the V_g sweep speed on the same order as τ, but it is not observed if the V_g sweep speed is very high (not shown in the figure). Therefore, the steep SS is not realized only by the nonlinear dielectric constant of FE. The dynamics of polarization plays a key role in the steep SS and will determine and limit the operation speed of NCFET, as demonstrated in Fig. 26(d). It was pointed out that the nonlinearity of the FET substrate capacitance also plays an important role in the steep SS in the deep subthreshold region because a small depletion layer capacitance induces a large depolarizing field in the FE capacitor in the transition from the accumulation or inversion region.¹¹¹⁾

The operation principle of NCFET based on the polarization switching delay model described above is summarized in Fig. 30,¹¹²⁾ which illustrates the operation points and corresponding band diagrams of NCFET. After initializing NCFET by a negative V_g, NCFET transitions from accumulation to depletion [Fig. 30(a)]. The depletion capacitance in the subthreshold region causes a large voltage drop in the substrate and a large depolarizing field in the FE layer by polarization switching, which results in a transient NC effect seen as a voltage snapback [Fig. 30(b)]. Ψ_s is temporarily amplified and SS becomes small. In the inversion region, NCFET has a typical voltage divider between the gate insulator and the substrate capacitance, and Ψ_s is not amplified [Fig. 30(c)].

Note that hysteresis is, in principle, inevitable in this model unless a gate insulator is negligibly thin or charge injection compensates the V_th shift. V_fe must pass V_c, which may restrict the use of NCFET for low-voltage operation. A steep SS can be observed in a wider I_d range in backward sweep because the transient NC effect occurs in the transition from the inversion region to the subthreshold region. Moreover, the NC effect can only be observed in the bipolar switching mode, while unipolar switching does not show the NC effect, as shown in Fig. 28(c),¹⁰⁷⁾ which is why the initialization of polarization by a large negative bias is needed before polarization switching in experiments.

To realize a steep SS at a high speed such as in the GHz range, polarization switching delay should be orders of magnitude shorter, which coincides with the conclusions based on the Landau free energy model in Sect. 3.4.1, although the physical origin of the NC effect is different. Since FE-HfO₂ is known to contain a substantial number of defects, controlling and reducing the number of those defects will be helpful for hastening the domain switching. As mentioned in Sect. 3.4.1, a more accurate high-speed measurement will be needed to extract intrinsic dynamic parameters in a nanoscale capacitor or transistor excluding parasitic components as much as possible. A standard quasi-static parametric I_d–V_g test may not be appropriate for fast NCFET as the V_g sweep speed is very low compared with τ based on the model above. A new test method for estimating a steep SS will be needed other than ring oscillator measurement.

5. Summary

In this paper, the original concept and early works on NCFET were overviewed. Recent studies on NCFET were also reviewed, especially after the discovery of FE-HfO₂. Several device options such as gate stack and channel engineering were explained. Device considerations were discussed in terms of operation speed, scalability, SCE, reliability, and variability. The NC effect can be an effective performance booster at a low cost with the use of FE-HfO₂. A recent demonstration of 14 nm NC FinFET has proved the feasibility of NCFET and attracted much attention of device researchers and engineers. Although the original NCFET model was proposed as static, the model is now reconsidered as dynamic on the basis of the classical ferroelectric model with a nonlinear capacitor and resistance, and polarization switching delay, which may restrict the applicability of NCFET. For NCFET to become a manufacturable transistor solution to extend CMOS scaling, further research and development will be needed to address and tackle the challenges discussed in this paper.

Acknowledgments

The author wishes to thank Professor Toshiro Hiramoto for technical support and discussions. The author also wishes to thank Kyungmin Jang, Chengji Jin, Nozomu Ueyama, Yusaku Tagawa, Tomoko Mizutani, Waichi Nagashiro, and Takuya Saraya for their contributions to this work, and Dr. Takashi Ando, Dr. Martin Frank, and Dr. Paul Solomon of IBM Watson Research Center for discussions. This work was supported by JST PRESTO Grant Number JPMJPR1525 and JSPS KAKENHI Grant Number 16K18085. This work was also supported by Tokyo Electron Ltd.