Abstract
A procedure to construct an MOS LSI fabrication process, using direct electron beam writing technology, has been proposed. Positive resist PMMA and aluminum liftoff technique are used. Proximity effect and resist thickness dependence, as well as line width and undercut profile of resist patterns, play important roles in determination of optimum patterning condition. Electron beam radiation damage can be annealed out by suitable heat-treatment, while the amount of damage depends on processing steps. The process also includes a plasma etching with improved gas composition, a two-step glass flow technique and molybdenum wet etching with newly developed solution. Successful fabrication results, 1-kbit MOS RAM and TEG with 2 µm minimum pattern dimension, demonstrate the validity of these processes.